International Journal of Innovative Research and Development

Abstract

The low-voltage CMOS differential logic operating with supply voltage approaching the MOS threshold voltage. The logic style which is proposed improves switching speed. It has been done boosting the gate–source voltage of transistors along timing-critical signal paths. This logic style minimizes area overhead which is achieved by using the single boosting circuit is shared by complementary outputs. The proposed logic style improves Energy delay product compared with conventional logic styles. The supply voltage scales down toward the threshold voltage, the speed performance of conventional CMOS circuits, such as static CMOS logic, differential cascode voltage switch (DCVS) logic and domino CMOS logic is still severely degraded due to the reduced overdrive voltage (VGS − VTH) of transistors. To overcome this Problem, a bootstrapped CMOS large capacitive-load driver was proposed CMOS bootstrapped dynamic logic (BDL) was proposed. However, the speed of this logic style was not so much improved since the latency of bulky bootstrapping circuit was superimposed on the overall latency of the circuit. To overcome the   problems and to further improve the switching performance, Boosting CMOS differential logic style is proposed .The BCDL provides higher switching speed than the conventional logic style at low supply voltage. The BCDL also minimizes area overhead by allowing a single boosting circuit to be shared by complementary outputs. The experimental result for Ripple Carry Adder using BCDL design with the proposed logic style.

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