International Journal of Innovative Research and Development

Abstract

In this article we propose the design of a GALS wrapper used in Network on Chip (NoC) based on standard cells. The GALS packaging embrace two announcement docks, 4-phase grasp circuits, records buffer and pointer synchronizer. The detailed aim of GALS wrapper is given and the circuits are verified with Verlog-HDL and executed in FPGA. The verified results shows that the wrapper provides fast and consistent communication for the subsystems working with different clocks of NoC.

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