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DFAL Based Flexible Multi-Modulo Prescaler


Affiliations
1 Department of Electronics and Communication Engineering, Delhi Technological University, India
2 Department of Electronics and Communication Engineering, Bharati Vidyapeeth’s College of Engineering, India
     

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The quest to have longer battery life and reduced packaging cost has been motivating factor behind developing low power circuits for different applications. Research in adiabatic logic has recently gained momentum and diode free adiabatic logic (DFAL) is one among promising variant. This paper presents a diode free adiabatic logic (DFAL) based flexible multi-modulo prescaler. It provides frequency division of 32, 33, 47, 48, 64, 65, 79 and 80 based upon the value of control signals. The functionality and performance of the proposed prescaler is investigated through TSPICE simulations by using 0.18 micron TSMC technology parameters. The performance parameters average power dissipation, time delay and PDP of the DFAL based circuit are compared with its static CMOS counterpart and a maximum power saving of 84.6% is achieved.

Keywords

CMOS, DFAL, Dual-Modulo Prescaler, Multi-Modulo Prescaler.
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  • DFAL Based Flexible Multi-Modulo Prescaler

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Authors

Nitish
Department of Electronics and Communication Engineering, Delhi Technological University, India
Neeta Pandey
Department of Electronics and Communication Engineering, Delhi Technological University, India
Kirti Gupta
Department of Electronics and Communication Engineering, Bharati Vidyapeeth’s College of Engineering, India
Manu Kumar Saini
Department of Electronics and Communication Engineering, Delhi Technological University, India

Abstract


The quest to have longer battery life and reduced packaging cost has been motivating factor behind developing low power circuits for different applications. Research in adiabatic logic has recently gained momentum and diode free adiabatic logic (DFAL) is one among promising variant. This paper presents a diode free adiabatic logic (DFAL) based flexible multi-modulo prescaler. It provides frequency division of 32, 33, 47, 48, 64, 65, 79 and 80 based upon the value of control signals. The functionality and performance of the proposed prescaler is investigated through TSPICE simulations by using 0.18 micron TSMC technology parameters. The performance parameters average power dissipation, time delay and PDP of the DFAL based circuit are compared with its static CMOS counterpart and a maximum power saving of 84.6% is achieved.

Keywords


CMOS, DFAL, Dual-Modulo Prescaler, Multi-Modulo Prescaler.