VLSI Implementation of High Speed Area Efficient Arithmetic Unit Using Vedic Mathematics

High speed Arithmetic Units (AUs) are widely used in architectures used in signal and image processing applications. AUs involve multi-functions and have multiplier as the critical element. In this paper, we present design and implementation of high speed and area efficient AU using Vedic algorithm. The work uses a simple “vertical and crosswise sutra” of Vedic mathematics to produce low complexity Partial Product (PP) generation unit in multiplier which reduces critical delay. Implementation results using TSMC 180 nm CMOS process with CADENCE Encounter Digital Implementation of the proposed AU revealed delay and Area-Delay Product (ADP) reductions of 13.7% and 19.2% respectively compared to prior recent approaches.