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Design and Implementation of High Speed Latched Comparator Using gm/Id Sizing Method


Affiliations
1 Automotive Infotainment Systems, Microchip Technology Pvt. Ltd., India
2 School of Electrical Engineering and Computing, Addis Ababa Science and Technology University, Ethiopia
     

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Design of an analog circuit depends on several factors such as design methodology, good modeling and technology characterization. This work focuses on designing a high speed (1.6GHz) latched comparator with low power consumption suitable for ADCs in SoC applications. The latched comparator is designed with StrongArm latch as the primary decision and amplification stage followed by a latching element to drive the output load. The StrongArm latch is a proven circuit topology suitable for all seasons. The zero static power consumption of StrongArm latch is exploited to design a low power comparator. The output latch is used to hold the previous output value during the tracking time of the comparator. The designed comparator achieves zero setup time at a clock frequency of 1.6GHz and produces digital output with a maximum delay of 180ps.The comparator is implemented with SAED 32nm technology libraries. The performance has been analyzed using HSPICE simulator.

Keywords

Latched Comparator, Strong Arm Latch, High Speed, Low Power.
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  • Design and Implementation of High Speed Latched Comparator Using gm/Id Sizing Method

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Authors

R. Vinoth
Automotive Infotainment Systems, Microchip Technology Pvt. Ltd., India
S. Ramasamy
School of Electrical Engineering and Computing, Addis Ababa Science and Technology University, Ethiopia

Abstract


Design of an analog circuit depends on several factors such as design methodology, good modeling and technology characterization. This work focuses on designing a high speed (1.6GHz) latched comparator with low power consumption suitable for ADCs in SoC applications. The latched comparator is designed with StrongArm latch as the primary decision and amplification stage followed by a latching element to drive the output load. The StrongArm latch is a proven circuit topology suitable for all seasons. The zero static power consumption of StrongArm latch is exploited to design a low power comparator. The output latch is used to hold the previous output value during the tracking time of the comparator. The designed comparator achieves zero setup time at a clock frequency of 1.6GHz and produces digital output with a maximum delay of 180ps.The comparator is implemented with SAED 32nm technology libraries. The performance has been analyzed using HSPICE simulator.

Keywords


Latched Comparator, Strong Arm Latch, High Speed, Low Power.

References