Open Access
Subscription Access
Open Access
Subscription Access
A Case Study on Cluster Based Power-Aware Mapping Strategy for 2D NoC
Subscribe/Renew Journal
Network on Chip (NoC) is a growing and prominent paradigm which improves the power and performance of the System on Chip (SoC). Application mapping is one of the major challenges in NoC which maps the various Intellectual Property (IP) cores to standard network topology. Among the various application mapping methods, Integer Linear programming (ILP) is one of the static mapping methods, which finds optimum communication cost. However, it consumes longer computation time. To overcome this limitation, cluster based mapping using KL algorithm has been introduced and it acts poorly at partitioning cut degree. Based on these studies, we propose Fidducia-Mattheyses (FM) algorithm for multi clustering to optimize power consumption and communication cost for different benchmarks of NoC. The effectiveness of the proposed method is verified through VOPD, MPEG 4 and PIP benchmarks. Experimental results show a 4.4% and 34% improvement on communication cost and power consumption respectively for FM algorithm with MPEG 4. However, for VOPD the communication cost and total power consumption is improved with 27% and 35% respectively. On the other hand, PIP benchmark offers identical results in total power consumed and communication cost minimization with existing methods.
Keywords
Application Mapping, Integer Linear Programming (ILP), Cluster Based Mapping, Fidducia-Mattheyses (FM) Algorithm.
Subscription
Login to verify subscription
User
Font Size
Information
- Wen-Chung Tsai, Ying Cherng Lan, Yu Hen Hu and Sao Jie Chen, “Networks on Chips: Structure and Design Methodologies”, Journal of Electrical and Computer Engineering, Vol. 2012, No. 2, pp. 1-15, 2012
- Tobias Bjerregaard and Shankar Mahadevan, “A Survey of Research and Practices of Network-on-Chip”, ACM Computing Surveys, Vol. 38, No. 1, pp. 1-51, 2006.
- Radu Marculescu et.al., “Outstanding Research Problems in NoC Design: System, Micro Architecture, and Circuit Perspectives”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 2009, pp. 3-21, 2009.
- Pradip Kumar Sahu and Santanu Chattopadhyay, “A Survey on Application Mapping Strategies for Network-on-Chip Design”, Systems Architecture, Vol. 59, No. 1, pp. 60-76, 2013.
- Coskun Celdk and Cuneyt F. Bazlamacci, “Effect of Application Mapping on Network on Chip Performance”, Proceedings of IEEE International Conference on Parallel Distributed and Network based processing, pp. 465-472, 2012
- A. Aravindhan, S. Salini and G. Lakshminarayanan, “Cluster Based Application Mapping Strategy for 2D NoC”, Proceedings of 1st Global Colloquium on Recent Advancements and Effectual Researches in Engineering, Science and Technology, pp. 505-512, 2016.
- Suleyman Tosun, “New Heuristic Algorithms for Energy Aware Application Mapping and Routing on Mesh-based NoCs”, Systems Architecture, Vol. 57, No. 1, pp. 69-78, 2011.
- Coskun Celik and Cuneyt F. Bazlamacci, “Evaluation of Energy and Buffer Aware Application Mapping for Networks-on-Chip”, Microprocessors and Microsystems, Vol. 38, No. 4, pp. 325-336, 2014.
- Srinivasan Murali and Giovanni De Micheli, “Bandwidth-Constrained Mapping of Cores onto NoC Architectures”, Proceedings of the Conference on Design, automation and test in Europe, Vol. 2, pp. 20896, 2004.
- Coskun Celik and Cuneyt F. Bazlamacci, “Energy and Buffer Aware Application Mapping for Networks-on-Chip with Self Similar Traffic”, Systems Architecture, Vol. 59, No. 10, pp. 1364-1374, 2013.
- Suleyman Tosun, “Cluster-based Application Mapping Method for Network-on-Chip”, Advances in Engineering Software, Vol. 42, No. 10, pp. 868-874, 2011.
- Haytham Elmiligi et.al., “Power Optimization for Application-Specific Networks-on-Chips: A Topology-based Approach”, Microprocessors and Microsystems, Vol. 33, No. 5-6, pp. 343-355, 2009.
- Suleyman Tosun, Ozcan Ozturk and Meltem Ozen,. “An ILP Formulation for Application Mapping onto Network-on-Chip”, Proceedings of 3rd International Conference on Application of Information and Communication Technologies, pp. 1-5, 2009.
- D.T. Nguyen, Y. Bai, J. Qin, B. Han and Y. Hu, “Computational aspects of Linear Programming Simplex Method”, Advances in Engineering Software, Vol. 31, No. 8-9, pp. 539-545, 2000.
- B. W. Kernighan and S. Lin, “An Efficient Heuristic Procedure for Partitioning Graphs”, The Bell System Technology Journal, Vol. 49, No. 2, pp. 291-307, 1972.
- Charalampos Papamanthou, “Depth First Search and Directed Acyclic Graphs”, Department of Computer Science, University of Crete, pp. 1-27, 2004.
- Andrew B. Kahng, Jens Lienig, Igor L. Markov and Jin Hu, “VLSI Physical Design: From Graph Partitioning to Timing Closure”, Springer Science and Business Media, 2011.
- Sadiq M. Sait and Habib Youssef , “VLSI Physical Design Automation: Theory and Practice”, World Scientific Publishing, 1999.
- Elyas Khajekarimi and Mahmoud Reza Hashemi, “Energy-Aware ILP Formulation for Application Mapping on NoC based MPSoCs”, Proceedings of 21st Iranian Conference on Electrical Engineering, pp. 1-5, 2013.
- Tero Harju, “Lecture Notes on Graph Theory, Department of Mathematics”, Available at: http://cs.bme.hu/fcs/graphtheory.pdf.
- Asrani Hj Lit, Siti Kudnie Sahari, Rohana Sapawi and Ahmad Fariz Hasan, “Power Optimization for Mesh Network-on-Chip Architecture: Multi-level Network Partitioning Approach”, Proceedings of 6th Engineering Conference, Energy and Environment, pp. 1-5, 2013.
- Predictive Technology Model Available at: http://ptm.asu.edu/
Abstract Views: 397
PDF Views: 1