Open Access
Subscription Access
Open Access
Subscription Access
Parametric Analysis of DFAL Based Dynamic Comparator
Subscribe/Renew Journal
In Complementary Metal Oxide Semiconductor (CMOS) technology, the advancement in manufacturing of semiconductor processing has changed the designing challenges for the researchers. The challenges that are now being vital are high speed and low power computing devices. This paper presents a novel dynamic comparator with DFAL (Diode Free Adiabatic Logic) inverter that employs the principle of adiabatic logic. As compared to the conventional CMOS technique, the adiabatic logic technique shows more promising results. The proposed Dynamic Comparator, not only provides low power consumption and reduces the delay, but also improves the energy efficiency in comparison to the conventional Dynamic Comparator. The design has been simulated using Cadence Virtuoso Spectre simulator in gdpk 90nm Technology.
Keywords
Conventional Dynamic Comparator, Adiabatic Logic, DFAL Inverter, Low Power.
Subscription
Login to verify subscription
User
Font Size
Information
- V. Deepika and Sangeeta Singh, “Design and Implementation of A Low Power, High Speed Comparator”, Procedia Materials Science, Vol. 10, pp. 314-322, 2015.
- Jun He, Sanyi Zhan, Degang Chen and Randall L. Geiger, “Analyses of Static and Dynamic Random Offset Voltages in Dynamic Comparators”, IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 56, No. 5, pp. 911-919, 2009.
- Islam T. Abougindia, Ismail Cevik, Fadi N. Zghoul and Suat U. Ay, “A Precision Comparator Design with A New Foreground Offset Calibration Technique”, Analog Integrated Circuits and Signal Processing, Vol. 83, No. 2, pp. 243-255, 2015.
- Takayuki Okazawa, Ippei Akita and Makoya Ishida, “A Digitally Calibrated Dynamic Comparator using Time-Domain Offset Detection”, Analog Integrated Circuits and Signal Processing, Vol. 81, No. 3, pp. 561-570, 2014.
- Masaya Miyahara, Yusuke Asada, Daehwa Paik and Akira Matsuzawa, “A Low-Noise Self-Calibrating Dynamic Comparator for High-Speed ADCs”, Proceedings of IEEE Asian Solid-State Circuits Conference, pp. 269-272, 2008.
- N.H.E. Weste and D. Harris, “CMOS VLSI Design: A Circuits and Systems Perspective”, 3rd Edition, Pearson Education, 2011.
- Philip Teichmann, “Fundamentals of Adiabatic Logic”, Adiabatic Logic, Vol. 34, pp. 5-22, 2012.
- Irfan Ahmad Pindoo, Tejinder Singh, Amritpal Singh, Ankit Chaudhary and P. Mohan Kumar, “Power Dissipation Reduction Using Adiabatic Logic Techniques for CMOS Inverter Circuit”, Proceedings of IEEE 6th International Conference on Computing, Communication and Networking Technologies, pp. 1-6, 2015.
- Yong Moon and Deog Kyoon Jeong, “An Efficient Charge Recovery Logic Circuit”, IEEE Journal of Solid-State Circuits, Vol. 31, No. 4, pp. 514-522, 1996.
- Yibin Ye and Kaushik Roy, “QSERL: Quasi-Static Energy Recovery Logic”, IEEE Journal of Solid-state Circuits, Vol. 36, No. 2, pp. 239-248, 2001.
- N. Anuar, Y. Takahashi and T. Sekine, “Two Phase Clocked Adiabatic static CMOS Logic and its Logic Family”, Journal of Semiconductor Technology and Science, Vol. 10, No. 1, pp. 1-10, 2010.
- Shipra Upadhyay, R.A. Mishra, R.K. Nagaria and S.P. Singh, “DFAL: Diode-Free Adiabatic Logic Circuits”, ISRN Electronics, Vol. 2013, pp. 1-12, 2013.
- Heena Parveen and Vishal Moyal, “Implementation of Low Power Adiabatic based Inverter for Dynamic Comparator”, International Journal of Science and Research, Vol. 6, No. 1, pp. 2320-2323, 2017.
Abstract Views: 215
PDF Views: 1