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Parametric Analysis of DFAL Based Dynamic Comparator
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In Complementary Metal Oxide Semiconductor (CMOS) technology, the advancement in manufacturing of semiconductor processing has changed the designing challenges for the researchers. The challenges that are now being vital are high speed and low power computing devices. This paper presents a novel dynamic comparator with DFAL (Diode Free Adiabatic Logic) inverter that employs the principle of adiabatic logic. As compared to the conventional CMOS technique, the adiabatic logic technique shows more promising results. The proposed Dynamic Comparator, not only provides low power consumption and reduces the delay, but also improves the energy efficiency in comparison to the conventional Dynamic Comparator. The design has been simulated using Cadence Virtuoso Spectre simulator in gdpk 90nm Technology.
Keywords
Conventional Dynamic Comparator, Adiabatic Logic, DFAL Inverter, Low Power.
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