ICTACT Journal on Microelectronics

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FPGA Implementation of LSB-MR Based Steganography Algorithms


Affiliations
1 Department of Elecctronics and Communication Engineering, Mepco Schlenk Engineering College, India
     

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In network security Image Steganography is one of the crucial data hiding technique. In this paper a new architecture was proposed for with and without pipelining technique for LSB Matching Revisited steganography algorithm and it is implemented in FPGA using Verilog HDL. The design motto is to increasing the speed, reducing the clock cycle by performing embedded and fetching operation parallel, reduces the complexity in both transmitting and receiving side and also we can send more confidential message due to the large cover image (128×128×8) size which we have used here. In the transmitting side data hiding is performed and receiving side extraction is performed. Whole entire process is takes place in both hardware and software, finally, result was analysed for both software and hardware level. From the outcome investigation, Pipelined model will give a superior outcome while contrasting with non-pipelining mode as far as less inserting time contrasted with the non-pipelined mode.

Keywords

Verilog HDL, LSBMR, FPGA, Pipelining.
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  • Michael Schaeferling et al., “ASTERICS An Open Toolbox for Sophisticated FPGA-Based Image Processing”, Proceedings of International Embedded World Conference, pp. 1-8, 2015.

  • M.S. Sutaone and M.V. Khandare, “Image based Steganography using LSB Insertion Technique”, Proceedings of IET International Conference on Wireless, Mobile and Multimedia Networks, pp. 146-151, 2008.

  • Weiqi Luo, Fangjun Huang and Jiwu Huang, “Edge Adaptive Image Steganography Based on LSB Matching Revisited”, IEEE Transactions on Information Forensics and Security, Vol. 5, No. 2, pp. 201-124, 2010.

  • J. Mielikainenm, “LSB Matching Revisited”, IEEE Signal Processing Letters, Vol. 13, No. 5, pp. 285-287, 2006.

  • Da-Chun Wu and Wen-Hsiang Tsai, “A Steganographic Method for Images by Pixel-Value Differencing”, Pattern Recognition Letters, Vol. 24, No. 9-10, pp. 1613-1626, 2003.

  • Cheng-Hsing Yang, Chi-Yao Weng, Shiuh-Jeng Wang and Hung Min Sun, “Adaptive Data Hiding in Edge Areas of Images with Spatial LSB Domain Systems”, IEEE Transactions on Information Forensics and Security, Vol. 3, No. 3, pp. 488-497, 2008.

  • Kh. Manglem Singh, L. Shyamsudar Singh, A. BubooSingh and Kh. Subhabati Devi, “Hiding Secret Message in Edges of the Image”, Proceedings of International Conference on Information and Communication Technology, pp. 238-241, 2007.

  • Kathryn Hempstalk, “Hiding behind Corners: using Edges in Images for Better Steganography”, Proceedings of Computing Women’s Congress, pp. 1-3, 2006.

  • J. Mielikainen, “LSB Matching Revisited”, IEEE Signal Processing Letters, Vol. 13, No. 5, pp. 285-287, 2006.

  • X. Li, B. Yang, D. Cheng and T. Zeng, “A Generalization of LSB Matching”, IEEE Signal Processing Letters, Vol. 16, No. 3, pp. 69-72, 2009.

  • Z. Weiming, Z. Xinpeng and W. Shuozhong, “A Double Layered Data Embedding Scheme”, IEEE Signal Processing Letters, Vol. 14, No. 11, pp. 848-851, 2007.

  • Carlos Gonzalez et al., “Use of FPGA or GPU-based Architectures for Remotely Sensed Hyper Spectral Image Processing”, Integration the VLSI journal, Vol. 46, No. 2, pp. 89-103, 2013.


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  • FPGA Implementation of LSB-MR Based Steganography Algorithms

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Authors

K. Nandhini
Department of Elecctronics and Communication Engineering, Mepco Schlenk Engineering College, India
S. Arivazagan
Department of Elecctronics and Communication Engineering, Mepco Schlenk Engineering College, India

Abstract


In network security Image Steganography is one of the crucial data hiding technique. In this paper a new architecture was proposed for with and without pipelining technique for LSB Matching Revisited steganography algorithm and it is implemented in FPGA using Verilog HDL. The design motto is to increasing the speed, reducing the clock cycle by performing embedded and fetching operation parallel, reduces the complexity in both transmitting and receiving side and also we can send more confidential message due to the large cover image (128×128×8) size which we have used here. In the transmitting side data hiding is performed and receiving side extraction is performed. Whole entire process is takes place in both hardware and software, finally, result was analysed for both software and hardware level. From the outcome investigation, Pipelined model will give a superior outcome while contrasting with non-pipelining mode as far as less inserting time contrasted with the non-pipelined mode.

Keywords


Verilog HDL, LSBMR, FPGA, Pipelining.

References