ICTACT Journal on Microelectronics

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FPGA Implementation of LSB-MR Based Steganography Algorithms


Affiliations
1 Department of Elecctronics and Communication Engineering, Mepco Schlenk Engineering College, India
     

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In network security Image Steganography is one of the crucial data hiding technique. In this paper a new architecture was proposed for with and without pipelining technique for LSB Matching Revisited steganography algorithm and it is implemented in FPGA using Verilog HDL. The design motto is to increasing the speed, reducing the clock cycle by performing embedded and fetching operation parallel, reduces the complexity in both transmitting and receiving side and also we can send more confidential message due to the large cover image (128×128×8) size which we have used here. In the transmitting side data hiding is performed and receiving side extraction is performed. Whole entire process is takes place in both hardware and software, finally, result was analysed for both software and hardware level. From the outcome investigation, Pipelined model will give a superior outcome while contrasting with non-pipelining mode as far as less inserting time contrasted with the non-pipelined mode.

Keywords

Verilog HDL, LSBMR, FPGA, Pipelining.
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  • Michael Schaeferling et al., “ASTERICS An Open Toolbox for Sophisticated FPGA-Based Image Processing”, Proceedings of International Embedded World Conference, pp. 1-8, 2015.

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  • FPGA Implementation of LSB-MR Based Steganography Algorithms

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Authors

K. Nandhini
Department of Elecctronics and Communication Engineering, Mepco Schlenk Engineering College, India
S. Arivazagan
Department of Elecctronics and Communication Engineering, Mepco Schlenk Engineering College, India

Abstract


In network security Image Steganography is one of the crucial data hiding technique. In this paper a new architecture was proposed for with and without pipelining technique for LSB Matching Revisited steganography algorithm and it is implemented in FPGA using Verilog HDL. The design motto is to increasing the speed, reducing the clock cycle by performing embedded and fetching operation parallel, reduces the complexity in both transmitting and receiving side and also we can send more confidential message due to the large cover image (128×128×8) size which we have used here. In the transmitting side data hiding is performed and receiving side extraction is performed. Whole entire process is takes place in both hardware and software, finally, result was analysed for both software and hardware level. From the outcome investigation, Pipelined model will give a superior outcome while contrasting with non-pipelining mode as far as less inserting time contrasted with the non-pipelined mode.

Keywords


Verilog HDL, LSBMR, FPGA, Pipelining.

References