Error Compensation Technique for 90nm CMOS Fixed-Width and Area Efficient Booth Encoding Multiplier

An area efficient, fixed width multiplier using booth encoding is done in this work. The work is further extended to accommodate the error correction feature. As in many signal processing products fast and efficient processing elements are required, the demand increases day by day. This work is one such finding to meet the standard of today’s contemporary technology. The proposed methodology suits well for the discrete cosine transform application. A new multiplier architecture using booth encoding is done. The architecture includes a tree based carry save reduction unit with parallel prefix adder and the compensation circuit. The work is carried out in 180nm technology using predictive technology models. The circuits are implemented using SPICE models and the results are obtained. For equal probability the inputs of different blocks are kept ‘1’ or ‘0’ in equal numbers. The frequency of operation is 100MHz. The proposed design will be compared with the existing methods. The robustness will be checked using skewed distribution. The project will be further extended to design for high speed and advanced technology of 90nm in future.