Ultra Low Power and Secure VLSI Architecture for Dedicated Short Range Communication Applications

Dedicated Short Range Communication (DSRC) is being widely deployed in intelligent transportation systems. The DSRC standards typically choose to take up line codes such as Manchester, differential Manchester, and FM0 codes to achieve dc balance. In this paper, low power and secure VLSI architecture for integrated codes is proposed. The performance of the circuit is evaluated using 18nm FinFET based ECRL adiabatic logic in Cadence tool. The average power dissipation of multimode encoder operating at 877.192MHz is observed to be 32.24 μw. The design provides not only 100% hardware utilization rate (HUR) but also maximum power saving of 99.99% over reported values for FPGA implementation. The adiabatic logic circuits designed with ECRL exhibit uniform peak current traces and hence are able to withstand differential power analysis (DPA) attacks, thereby offering improved security performance of the circuit.