Comparative Analysis of Various Approximate Full Adders under RTL Codes

Approximate or inexact computing is a well-established paradigm for designing error-tolerant applications such as image and digital signal processing. It is an interesting area of research, especially in the computer arithmetic designs. One key feature of this technique is that it reduces accuracy but still provides meaningful results with low power and reduced circuit complexity. This paper presents a comparative analysis of state-of-the-art approximate 1-bit full adders (AFA) for inexact computation. The performance of these AFAs are compared in terms of the design metrics (DMs) such as power, delay, and area. For a fair comparison, all AFAs under consideration have been described in Verilog register-transfer-level (RTL) codes and synthesized using Cadence’s RTL compiler. The synthesis is carried out using Cadence’s 180 nm standard cell library.