ICTACT Journal on Microelectronics

Open Access Open Access  Restricted Access Subscription Access
Open Access Open Access Open Access  Restricted Access Restricted Access Subscription Access

An Improved Nanoscale Quasi-Ballistic Double Gate (DG) Mosfet Model with Drain Bias Dependency on Critical Channel Length Near The Low Field Source Region by Semi-Empirical Approach


Affiliations
1 Department of Electronics and Communication Engineering, Shri Dharmasthala Manjunatheshwara College of Engineering and Technology, India
     

   Subscribe/Renew Journal


This work presents a physically accurate drain current model valid for Double Gate MOSFETs in the nanoscale regime. The model incorporates both diffusive and ballistic carrier transport on the basis of scattering theory. The significance of carrier scattering at the critical channel length near the low field source region is illustrated. The proposed model presents a semi-empirical approach to determine the critical channel length as a function of drain bias applicable for symmetric Double Gate MOSFETs. Fermi-Dirac statistics and Carrier degeneracy are considered in this work for optimal physical accuracy. The proposed quasi-ballistic model captures the signature effect of short channel devices and also exhibits good continuity in terms of drain current, terminal charges and capacitances. A relative analysis of the proposed quasi-ballistic model is done with other recent works.

Keywords

Diffusion, Quasi-Ballistic Transport, Scattering, Critical Channel Length, DG MOSFETs.
Subscription Login to verify subscription
User
Notifications
Font Size

  • D.J. Frank, R.H. Dennard, E. Nowak, P.M. Solomon, Y. Taur and H.P. Wong, “Device Scaling Limits of Si MOSFETs and their Application Dependencies”, Proceedings of IEEE, Vol. 89, No. 3, pp. 259-288, 2001.

  • D.J. Frank, S.E. Laux and M.V. Fischetti, “Monte Carlo Simulation of a 30 nm Dual-Gate MOSFET: How Short Can Si Go?”, Proceedings of International Conference on Electron Devices Meeting, pp.553-556, 1992.

  • H.C. Pao and C.T. Sah, “Effects of Diffusion Current on Characteristics of Metal-Oxide (Insulator)-Semiconductor Transistors (MOST)”, Solid-State Electronics, Vol. 9, No. 10, pp. 927-937, 1966.

  • J.R. Brews, “A Charge Sheet Model of the MOSFET”, Solid-State Electronics, Vol. 21, No. 2, pp. 345-355, 1987.

  • H.K.J. Ihantola and J.L. Moll, “Design Theory of a Surface Field-Effect Transistor”, Solid-State Electronics, Vol. 7, No. 6, pp. 423-430, 1964.

  • G. Gildenblat, X. Li, W. Wu, H. Wang and A. Jha, “PSP: An Advanced Surface-Potential-Based MOSFET Model for Circuit Simulation”, IEEE Transactions on Electron Devices, Vol. 53, No. 9, pp. 1979-1993, 2006.

  • Y. Taur, “An Analytical Solution to a Double-Gate Mosfet with Undoped Body”, IEEE Electron Device Letters, Vol. 21, No. 5, pp. 245-247, 2000.

  • Y.S. Chauhan, M.A. Karim, S. Venugopalan, S. Khandelwal, A. Niknejad and C. Hu, “BSIM6: Symmetric Bulk MOSFET Model”, Proceedings of International Conference on Nanotechnology, pp. 724-729, 2012.

  • Y. Taur and T.H. Ning, “Fundamentals of Modern VLSI Devices”, Cambridge University Press, 2009.

  • Y. Tsividis and C. McAndrew, “Operation and Modeling of the MOS Transistor”, Oxford Press, 2011.

  • A. Rahman, J. Guo, S. Datta, and M. Lundstrom, “Theory of Ballistic Nanotransistors”, IEEE Transactions on Electron Devices, Vol. 50, No. 9, pp.1853-1864, 2003.

  • M.S. Lundstrom and D.A. Antoniadis, “Compact Models and the Physics of Nanoscale FETs”, IEEE Transactions on Electron Devices, Vol. 61, No. 2, pp.225-233, 2014.

  • L. Wei, O. Mysore and D. A. Antoniadis, “Virtual-Source Based self-Consistent Current and Charge FET Models: From Ballistic to Drift Diffusion Velocity-Saturation Operation”, IEEE Transactions on Electron Devices, Vol. 59, No. 5, pp. 1263-1271,2012.

  • M. Lundstrom and J. Guo, “Nanoscale Transistors: Physics, Modeling, and Simulation”, Springer, 2006.

  • A. Khakifirooz, O.M. Nayfeh and D.A. Antoniadis, “A Simple Semi-Empirical Short-Channel MOSFET Current-Voltage Model Continuous Across all Regions of Operation and Employing only Physical Parameters”, IEEE Transactions on Electron Devices, Vol. 56, No. 8, pp. 1674-1680, 2009.

  • M. Lundstrom, “Elementary Scattering Theory of the Si MOSFET”, IEEE Electron Device Letters, Vol. 18, No. 7, pp.361-363, 1997.

  • M. Lundstrom and Z. Ren, “Essential Physics of Carrier Transport in Nanoscale MOSFETs”, IEEE Transactions on Electron Devices, Vol. 49, No. 1, pp.133-141, 2002.

  • Vyas Murnal and C. Vijaya, “A Quasi-Ballistic Drain Current, Charge and Capacitance Model with Positional Carrier Scattering Dependency Valid for Symmetric DG MOSFETs in Nanoscale Regime”, Nanoconvergence, Vol. 6, No. 19, pp. 1-17, 2019.

  • A. Rahman and M.S. Lundstrom, “A Compact Scattering Model for the Nanoscale Double-Gate MOSFET”, IEEE Transactions on Electron Devices, Vol. 49, No. 3, pp.481-489 2002.

  • K. Natori, “Ballistic Metal-Oxide-Semiconductor Field Effect Transistor”, Journal of Applied Physics, Vol. 76, pp.4879-4890, 1994.

  • J.S. Blakemore, “Approximations for Fermi-Dirac Integrals, Especially the function F (1⁄2) (n) used to Describe Electron Density in a Semiconductor”, Solid-State Circuits, Vol. 25, No. 11, pp. 1067-1076, 1982.

  • Y. Taur, X. Liang, W.Wang and H. Lu, “A Continuous, Analytic Drain Current Model for DG MOSFETs”, IEEE Transactions on Electron Devices, Vol. 25, No. 2, pp. 107-109, 2004.

  • B. Yu, H. Wang, A. Joshi, Q.E. Xiang and M.R. Lin, “15 nm Gate Length Planar CMOS Transistor”, Proceedings of International Electron Devices Meeting Technical Digest, pp. 1-8, 2001.

  • S. Datta, “Electronic Transport in Mesoscopic Structures”, Cambridge University Press, 1995.

  • D.J. Frank, Y. Taur and H.S.P. Wong, “Generalized Scale Length for Two-Dimensional Effects in MOSFETs”, IEEE Electron Device Letters, Vol. 19, No. 10, pp. 385-387, 1998.

  • Mathworks, Available at https://mathworks.com, Accessed at 2020.

  • S. Ahmed, S. Mehrotra, S. Kim, M. Mannino, G. Klimeck, D. Vasileska, X. Wang, H. Pal and G. Budiman, “MOSFet”, Available at https://nanohub.org/resources/mosfet, Accessed at 2020.

  • Mark R. Pinto and Kent Smith Padre, Available at https://nanohub.org/resources/padre, Accessed at 2020.

  • S. Khandelwal, H. Agarwal, P. Kushwaha, J.P. Duarte, A. Medury, Y.S. Chauhan, S. Salahuddin and C. Hu, “Unified Compact Model Covering Drift-Diffusion to Ballistic Carrier Transport”, IEEE Electron Device Letters, Vol. 37, No. 2, pp. 134-137, 2016.


Abstract Views: 338

PDF Views: 0




  • An Improved Nanoscale Quasi-Ballistic Double Gate (DG) Mosfet Model with Drain Bias Dependency on Critical Channel Length Near The Low Field Source Region by Semi-Empirical Approach

Abstract Views: 338  |  PDF Views: 0

Authors

Vyas R. Murnal
Department of Electronics and Communication Engineering, Shri Dharmasthala Manjunatheshwara College of Engineering and Technology, India
C. Vijaya
Department of Electronics and Communication Engineering, Shri Dharmasthala Manjunatheshwara College of Engineering and Technology, India

Abstract


This work presents a physically accurate drain current model valid for Double Gate MOSFETs in the nanoscale regime. The model incorporates both diffusive and ballistic carrier transport on the basis of scattering theory. The significance of carrier scattering at the critical channel length near the low field source region is illustrated. The proposed model presents a semi-empirical approach to determine the critical channel length as a function of drain bias applicable for symmetric Double Gate MOSFETs. Fermi-Dirac statistics and Carrier degeneracy are considered in this work for optimal physical accuracy. The proposed quasi-ballistic model captures the signature effect of short channel devices and also exhibits good continuity in terms of drain current, terminal charges and capacitances. A relative analysis of the proposed quasi-ballistic model is done with other recent works.

Keywords


Diffusion, Quasi-Ballistic Transport, Scattering, Critical Channel Length, DG MOSFETs.

References