ICTACT Journal on Microelectronics

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Design and Development of SOC Based Network on Chip Topologies


Affiliations
1 Department of Electronics and Communication Engineering, Osmania University, India
2 Department of Electronics and Communication Engineering, Vasavi College of Engineering, India
     

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The submicron technologies are revealing problems in the interconnections. Thus, the performance of the system largely depends on the structure of communication, in particular with regard to the flow, surface area and power consumed. In addition, traditional communications structures, which are generally based on shared buses, are limited in terms of performance. Indeed, they do not support high flow rates and they do not allow many elements to be interconnected, which makes them not very extensible. Based on this observation, several research groups have worked on a new form of interconnection adapted to future even more complex systems on a chip. They proposed the paradigm of networks on chip. In this paper, various SoC based network topologies has been implemented. Among various network topologies, the four well known topologies are selected. These selected four topologies are implemented by using Verilog programming language and corresponding results has been discussed.

Keywords

Network on Chip, Network Topologies, System on Chip, FPGA.
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  • Alak Majumder, Abir J. Mondal and Bidyut K. Bhattacharyya, “Threshold Adjustment of Receiver Chip to Achieve a Data Rate> 66 Gbit/Sec in Point-to-Point Interconnect”, Integration, Vol. 58, pp. 348-355, 2017.

  • Navaridas, Javier, Jose A. Pascual, Alejandro Erickson, Iain A. Stewart and Mikel Lujan. “INRFlow: An Interconnection Networks Research Flow-Level Simulation Framework”, Journal of Parallel and Distributed Computing, Vol. 130, pp. 140-152, 2019.

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  • Elie Duthoo and Olivier Mesnard, “CEA LIST: Processing Low-Resource Languages for CoNLL 2018”, Proceedings of International Conference on Shared Task: Multilingual Parsing from Raw Text to Universal Dependencies, pp. 34-44. 2018.

  • Stratis Ioannidis and Edmund Yeh, “Jointly Optimal Routing and Caching for Arbitrary Network Topologies”, IEEE Journal on Selected Areas in Communications, Vol. 36, No. 6, pp. 1258-1275, 2018.

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  • Miltos D. Grammatikakis, Riccardo Locatelli, Giuseppe Maruccia and Lorenzo Pieralisi, “Design of Cost-Efficient Interconnect Processing Units: Spiderg on STNoC”, CRC Press, 2020.

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  • John Kim, William J. Dally and Dennis Abts, “Flattened Butterfly: A Cost-Efficient Topology for High-Radix Networks”, Proceedings of Annual International Symposium on Computer Architecture, pp. 126-137, 2007.

  • Daifeng Zhang, and Haibin Duan, “Switching Topology Approach for UAV Formation based on Binary-Tree Network”, Journal of the Franklin Institute, Vol. 356, No. 2, pp. 835-859, 2019.


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  • Design and Development of SOC Based Network on Chip Topologies

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Authors

T. Nagalaxmi
Department of Electronics and Communication Engineering, Osmania University, India
E. Sreenivasa Rao
Department of Electronics and Communication Engineering, Vasavi College of Engineering, India
P. Chandrasekhar
Department of Electronics and Communication Engineering, Osmania University, India

Abstract


The submicron technologies are revealing problems in the interconnections. Thus, the performance of the system largely depends on the structure of communication, in particular with regard to the flow, surface area and power consumed. In addition, traditional communications structures, which are generally based on shared buses, are limited in terms of performance. Indeed, they do not support high flow rates and they do not allow many elements to be interconnected, which makes them not very extensible. Based on this observation, several research groups have worked on a new form of interconnection adapted to future even more complex systems on a chip. They proposed the paradigm of networks on chip. In this paper, various SoC based network topologies has been implemented. Among various network topologies, the four well known topologies are selected. These selected four topologies are implemented by using Verilog programming language and corresponding results has been discussed.

Keywords


Network on Chip, Network Topologies, System on Chip, FPGA.

References