ICTACT Journal on Microelectronics

Open Access Open Access  Restricted Access Subscription Access
Open Access Open Access Open Access  Restricted Access Restricted Access Subscription Access

Design and Development of SOC Based Network on Chip Topologies


Affiliations
1 Department of Electronics and Communication Engineering, Osmania University, India
2 Department of Electronics and Communication Engineering, Vasavi College of Engineering, India
     

   Subscribe/Renew Journal


The submicron technologies are revealing problems in the interconnections. Thus, the performance of the system largely depends on the structure of communication, in particular with regard to the flow, surface area and power consumed. In addition, traditional communications structures, which are generally based on shared buses, are limited in terms of performance. Indeed, they do not support high flow rates and they do not allow many elements to be interconnected, which makes them not very extensible. Based on this observation, several research groups have worked on a new form of interconnection adapted to future even more complex systems on a chip. They proposed the paradigm of networks on chip. In this paper, various SoC based network topologies has been implemented. Among various network topologies, the four well known topologies are selected. These selected four topologies are implemented by using Verilog programming language and corresponding results has been discussed.

Keywords

Network on Chip, Network Topologies, System on Chip, FPGA.
Subscription Login to verify subscription
User
Notifications
Font Size

  • Roberto Interdonato, Martin Atzmueller, Sabrina Gaito, Rushed Kanawati, Christine Largeron and Alessandra Sala, “Feature-Rich Networks: Going Beyond Complex Network Topologies”, Applied Network Science, Vol. 4, No. 1, pp. 1-13, 2019.

  • N. Prasad, Priyajit Mukherjee, SantanuChattopadhyay and Indrajit Chakrabarti, “Design and Evaluation of ZMesh topology for On-Chip Interconnection Networks”, Journal of Parallel and Distributed Computing, Vol. 113, pp. 17-36, 2018.

  • Alak Majumder, Abir J. Mondal and Bidyut K. Bhattacharyya, “Threshold Adjustment of Receiver Chip to Achieve a Data Rate> 66 Gbit/Sec in Point-to-Point Interconnect”, Integration, Vol. 58, pp. 348-355, 2017.

  • Navaridas, Javier, Jose A. Pascual, Alejandro Erickson, Iain A. Stewart and Mikel Lujan. “INRFlow: An Interconnection Networks Research Flow-Level Simulation Framework”, Journal of Parallel and Distributed Computing, Vol. 130, pp. 140-152, 2019.

  • Erwan Raffin, Ch Wolinski, François Charot, Krzysztof Kuchcinski, Stephane Guyetant, Stephane Chevobbe and Emmanuel Casseau, “Scheduling, Binding and Routing System for a Run-Time Reconfigurable Operator based Multimedia Architecture”, Proceedings of International Conference on Design and Architectures for Signal and Image Processing, pp. 168-175, 2010.

  • Elie Duthoo and Olivier Mesnard, “CEA LIST: Processing Low-Resource Languages for CoNLL 2018”, Proceedings of International Conference on Shared Task: Multilingual Parsing from Raw Text to Universal Dependencies, pp. 34-44. 2018.

  • Stratis Ioannidis and Edmund Yeh, “Jointly Optimal Routing and Caching for Arbitrary Network Topologies”, IEEE Journal on Selected Areas in Communications, Vol. 36, No. 6, pp. 1258-1275, 2018.

  • Travis Boraten and Avinash Karanth Kodi, “Runtime Techniques to Mitigate Soft Errors in Network-on-Chip (NoC) Architectures”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 37, No. 3, pp. 682-695, 2017.

  • Fawaz Alazemi, ArashAzizimazreah, Bella Bose and Lizhong Chen, “Routerless Network-on-Chip”, Proceedings of International Conference on High Performance Computer Architecture, pp. 492-503, 2018.

  • Eduardo Wachter, Luciano L. Caimi, ViniciusFochi, Daniel Munhoz and Fernando G. Moraes, “BrNoC: A Broadcast NoC for Control Messages in Many-Core Systems”, Microelectronics Journal, Vol. 68, pp. 69-77, 2017.

  • Jagadish B. Kotra, Haibo Zhang, Alaa R. Alameldeen, Chris Wilkerson and Mahmut T. Kandemir, “Chameleon: A Dynamically Reconfigurable Heterogeneous Memory System”, Proceedings of Annual IEEE/ACM International Symposium on Microarchitecture, pp. 533-545, 2018.

  • Qixun Zhang, Menglei Jiang, Zhiyong Feng, Wei Li, Wei Zhang and Miao Pan, “IoT Enabled UAV: Network Architecture and Routing Algorithm”, IEEE Internet of Things, Vol. 6, No. 2, pp. 3727-3742, 2019.

  • Santiago Segarra, Antonio G. Marques, Gonzalo Mateos and Alejandro Ribeiro, “Network Topology Inference from Spectral Templates”, IEEE Transactions on Signal and Information Processing over Networks, Vol. 3, No. 3, pp. 467-483, 2017.

  • Hui Jiang, Linjuan Sun, Juan Ran, JianxiaBai and Xiaoye Yang, “Community Detection Based on Individual Topics and Network Topology in Social Networks”, IEEE Access, Vol. 8, pp. 124414-124423, 2020.

  • Wai-Xi, Jun Cai, Qing Chun Chen and Yu Wang, “DRL-R: Deep Reinforcement Learning Approach for Intelligent Routing in Software-Defined Data-Center Networks”, Journal of Network and Computer Applications, Vol. 28, pp. 1-20, 2020.

  • Roberto Sanchez and Jean Pierre David, “Ultra-Low Latency Communication Channels for FPGA-based HPC Cluster”, Integration, Vol. 63, pp. 41-55, 2018.

  • Peter R.Monge, and Noshir S. Contractor, “Emergence of Communication Networks”, The New Handbook of Organizational Communication: Advances in Theory, Research, and Methods, pp. 440-502, 2001.

  • Wang Zhang, Ligang Hou, Jinhui Wang, ShuqinGeng and Wuchen Wu, “Comparison Research between XY and Odd-Even Routing Algorithm of a 2-Dimension 3x3 Mesh Topology Network-On-Chip”, Proceedings of Global Congress on Intelligent Systems, Vol. 3, pp. 329-333, 2009.

  • Sonal Yadav and Hemangee K. Kapoor, “Lightweight Message Encoding of Power-Gating Controller for On-Time Wakeup of Gated Router in Network-on-Chip”, Proceedings of International Symposium on Embedded Computing and System Design, pp. 1-6, 2019.

  • Mohsen Jahanshahi, and Fathollah Bistouni, “Crossbar-Based Interconnection Networks”, Series: Computer Communications and Networks, Vol. 12, pp. 164-173, 2018.

  • Ali Shokouhi, Marzieh Badkoobe, Farahnaz Mohanna, Ali Asghar Rahmani Hosseinabadi, and Arun Kumar Sangaiah, “Survey on Clustering in Heterogeneous and Homogeneous Wireless Sensor Networks”, The Journal of Supercomputing, Vol. 74, No. 1, pp. 277-323, 2018.

  • Fawaz Alazemi, Arash Azizimazreah, Bella Bose and Lizhong Chen, “Routerless Network-on-Chip”, Proceedings of IEEE International Symposium on High Performance Computer Architecture, pp. 492-503, 2018.

  • Kun Chih Chen, Masoumeh Ebrahimi, Ting Yi Wang and Yuch Chi Yang, “NoC-based DNN Accelerator: A Future Design Paradigm”, Proceedings of IEEE/ACM International Symposium on Networks-on-Chip, pp. 1-8. 2019.

  • Zhanserik Nurlan, Tamara Zhukabayeva and Mohamed Othman, “Mesh Network Dynamic Routing Protocols”, Proceedings of IEEE International Conference on System Engineering and Technology, pp. 364-369, 2019.

  • Akash Punhani, NeetuFaujdar and Sunil Kumar, “Design and Evaluation of Cubic Torus Network-on-Chip Architecture”, International Journal of Innovative Technology and Exploring Engineering, Vol. 8, No. 6, pp. 1672-1676, 2019.

  • Miltos D. Grammatikakis, Riccardo Locatelli, Giuseppe Maruccia and Lorenzo Pieralisi, “Design of Cost-Efficient Interconnect Processing Units: Spiderg on STNoC”, CRC Press, 2020.

  • Xueye Chen, Zhen Zhang, Dengli Yi and Zengliang Hu, “Numerical Studies on Different Two-Dimensional Micromixers Basing on a Fractal-Like Tree Network”, Microsystem Technologies, Vol. 23, No. 3, pp. 755-763, 2017.

  • John Kim, William J. Dally and Dennis Abts, “Flattened Butterfly: A Cost-Efficient Topology for High-Radix Networks”, Proceedings of Annual International Symposium on Computer Architecture, pp. 126-137, 2007.

  • Daifeng Zhang, and Haibin Duan, “Switching Topology Approach for UAV Formation based on Binary-Tree Network”, Journal of the Franklin Institute, Vol. 356, No. 2, pp. 835-859, 2019.


Abstract Views: 257

PDF Views: 0




  • Design and Development of SOC Based Network on Chip Topologies

Abstract Views: 257  |  PDF Views: 0

Authors

T. Nagalaxmi
Department of Electronics and Communication Engineering, Osmania University, India
E. Sreenivasa Rao
Department of Electronics and Communication Engineering, Vasavi College of Engineering, India
P. Chandrasekhar
Department of Electronics and Communication Engineering, Osmania University, India

Abstract


The submicron technologies are revealing problems in the interconnections. Thus, the performance of the system largely depends on the structure of communication, in particular with regard to the flow, surface area and power consumed. In addition, traditional communications structures, which are generally based on shared buses, are limited in terms of performance. Indeed, they do not support high flow rates and they do not allow many elements to be interconnected, which makes them not very extensible. Based on this observation, several research groups have worked on a new form of interconnection adapted to future even more complex systems on a chip. They proposed the paradigm of networks on chip. In this paper, various SoC based network topologies has been implemented. Among various network topologies, the four well known topologies are selected. These selected four topologies are implemented by using Verilog programming language and corresponding results has been discussed.

Keywords


Network on Chip, Network Topologies, System on Chip, FPGA.

References