![Open Access](https://i-scholar.in/lib/pkp/templates/images/icons/fulltextgreen.png)
![Restricted Access](https://i-scholar.in/lib/pkp/templates/images/icons/fulltextred.png)
![Open Access](https://i-scholar.in/lib/pkp/templates/images/icons/fulltextgreen.png)
![Open Access](https://i-scholar.in/lib/pkp/templates/images/icons/fulltext_open_medium.gif)
![Restricted Access](https://i-scholar.in/lib/pkp/templates/images/icons/fulltextred.png)
![Restricted Access](https://i-scholar.in/lib/pkp/templates/images/icons/fulltext_restricted_medium.gif)
FPGA Implementation of CSD Based NN Image Compression Architecture
Subscribe/Renew Journal
Complexity will be the critical issue in Very Large Scale Integration (VLSI) implementation of Image Compression Architectures. Especially it will be predominant issue while dealing with Neural Network (NN) based image compression architectures. Due to the development of Field-Programmable Gated Array (FPGA), dealing of NN Image Compression Architecture becomes smoother. Furthermore reducing power consumption of those architectures can be deal with Canonic Signed Digit (CSD) algorithms. NN based compression can be added to standard JPEG compression is proved be an efficient strategy for dealing images of high resolution in terms of speed and power. CSD algorithm is proved to provide low power consumption along with low computation time while dealing NN structures. The proposed architecture is hence based on CSD Floating Point Matrix Multiplier (FPMM) and it is synthesized and implemented using Xilinx Vivado Artix7 and Nexys DDR boards. Simulation with MATLAB & Xilinx Vivado is carried out for this work and almost same results are observed.
Keywords
CSD, FPMM, DDR, FPGA.
Subscription
Login to verify subscription
User
Font Size
Information
- Saudagar Abdul Khader Jilani and Syed Abdul Sattar, “JPEG Image Compression using FPGA with Artificial Neural Networks”, International Journal of Engineering Technology, Vol. 2, No. 3, pp. 252-257, 2010.
- Sampatrao L. Pinjare and E. Hemanth Kumar, “Implementation of Artificial Neural Network Architecture for Image Compression Using CSD Multiplier”, Proceedings of International Conference on Emerging Research in Computing, Information, Communication and Applications, pp. 1-13, 2019.
- Kaiyuan Guo, Shulin Zeng, Jincheng Yu, Yu Wang and Huazhong Yang, “A Survey of FPGA-Based Neural Network Inference Accelerator”, ACM Transactions on Intelligent Systems and Technology, Vol. 9, No. 4, pp. 1-26, 2017.
- Keshab K. Parhi, “VLSI Digital Signal Processing Systems: Design and Implementation”, Wiley, 1999.
- Lakshmi Kiran Mukkara and K. Venkata Ramanaiah, “CSD Based VLSI Architecture for NN Based Image Compression”, International Journal of Recent Technology and Engineering, Vol. 7, pp. 50-53, 2019.
- E.D. Kusuma and T.S. Widodo, “FPGA Implementation of Pipelined 2D-DCT and Quantization Architecture for JPEG Image Compression”, Proceedings of International Symposium on Information Technology, Vol. 1, pp. 1-6, 2010.
- A. Sindhuja and V. Sadasivam, “Wavelet based Segmentation using Optimal Statistical Features on Breast Images”, ICTACT Journal on Image and Video Processing, Vol. 4, No. 4, pp. 853-857, 2014.
- T. Pradeepthi and A.P. Ramesh, “Pipelined Architecture of 2D-DCT, Quantization and Zigzag Process for JPEG Image Compression using VHDL”, International Journal of VLSI Design and Communication Systems, Vol. 2, No. 3, pp. 99-105, 2011.
![](https://i-scholar.in/public/site/images/abstractview.png)
Abstract Views: 216
![](https://i-scholar.in/public/site/images/pdfview.png)
PDF Views: 0