ICTACT Journal on Microelectronics

Open Access Open Access  Restricted Access Subscription Access
Open Access Open Access Open Access  Restricted Access Restricted Access Subscription Access

Broadband CPW Fed Polarization Reconfigurable Antenna for Universal UHF RFID Reader


Affiliations
1 Department of Electronics and Communication Engineering, Andhra University College of Engineering, India
     

   Subscribe/Renew Journal


In this paper, a compact CPW fed polarization reconfigurable wideband antenna is presented for the application of a universal ultra-high frequency (UHF) radio frequency identification (RFID) antenna. In this work, long-range and random orientation detectability features are incorporated with the inclusion of polarization reconfigurability in the RFID reader antenna. Initially, a circularly polarized antenna is designed, which consists of a square slot embedded with an inverted L-shaped strip line and an F-shaped feeding structure, which is etched on the FR4_epoxy substrate. Secondly, the inclusion of three PIN diodes and an extra strip line connected to the feed structure are used to achieve linear as well as circular polarization. The desired performance is obtained in the whole UHF RFID frequency band (universally adopted range in the UHF band by the different countries) from 840 MHz to 960 MHz. Simulation, as well as experimentation procedures, are applied to obtain the details of the S11, gain, axial ratio, and radiation patterns. The experimented performance metrics are in good agreement with simulation results. The results reveal that axial ratio requirements for linear and circular polarizations are met in the required band of operation with accepTable.gain.

Keywords

RFID, Polarization Reconfigurable Antenna, CPW Feed, PIN Diodes, UHF Band.
Subscription Login to verify subscription
User
Notifications
Font Size

  • G. Hantos, D. Flynnand and M.P. Desmulliez, “Built-In Self-Test (BIST) Methods for MEMS: A Review”, Micromachines, Vol. 12, No. 1, pp. 1-28, 2021.

  • G. Karthy and P. Sivakumar, “Design of Modified March-C Algorithm and Built-In Self-Test Architecture for Memories”, Publicado en 3C Tecnologia, Vol. 34, pp. 219-229, 2020.

  • K. Gopalan and S. Pothiraj, “A Saboteur and Mutant based Built-in Self-Test and Counting Threshold-Based Built-in Self Repairing Mechanism for Memories”, Journal of Ambient Intelligence and Humanized Computing, Vol. 12, pp. 1-13, 2020.

  • A.M. Aswin and S. Sankar Ganesh, “Implementation and Validation of Memory Built in Self Test (MBIST) Survey”, International Journal of Mechanical Engineering and Technology, Vol. 10, No. 3, pp. 153-160,2019.

  • H. Sreenath and G. Narayanan, “FPGA Implementation of Pseudo Chaos-signal Generator for Secure Communication Systems”, Proceedings of International Conference on Advances in Computing, Communications and Informatics, pp. 804-807, 2018.

  • P.K. John, “BIST Architecture for Multiple RAMs in SoC”, Procedia Computer Science, Vol. 115, pp. 159-165, 2017.

  • B. Querbach, R. Khanna, S. Puligundla, D. Blankenbeckler, P. Chiang and J. Crop, “Architecture of a Reusable BIST Engine for Detection and Autocorrection of Memory Failures and for IO Debug, Validation, Link Training, and Power Optimization on 14-nm SoC”, IEEE Design and Test, Vol. 33, No. 1, pp. 59-67, 2016.

  • B. Mohammad, H. Saleh and M. Ismail, “Design Methodologies for Yield Enhancement and Power Efficiency in SRAM-Based SoCs”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 23, No. 10, pp. 2054-2064, 2015.

  • I. Pomeranz, “Computation of Seeds for LFSR-Based Diagnostic Test Generation”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 34, No. 12, pp. 2004-2012, 2015.

  • A. Kavitha and S. Sasi Kumar, “A Novel Two-Fold State Skip Logic Built-In Self-Test Scheme for Digital Circuits”, Computers and Electrical Engineering, Vol. 48, pp. 239-246, 2015.

  • V. Begam and S. Baulkani, “Ring Counter Based ATPG for Low Transition Test Pattern Generation”, The Scientific World Journal, Vol. 2015, pp. 1-6, 2015.

  • S. Vennelakanti and S. Saravanan, “Design and Analysis of Low Power Memory Built in Self-Test Architecture for SoC based Design”, Indian Journal of Science and Technology, Vol. 8, No. 14, pp.1-5, 2015.

  • G. Theodorou, N. Kranitis, A. Paschalis and D. Gizopoulos, “Software-Based Self-Test for Small Caches in Microprocessors”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 33, No. 12, pp. 1991-2004, 2014.

  • P. Dąbrowski, G. Łabuzek, T. Rachwalik and J. Szmidt, “Searching for Nonlinear Feedback Shift Registers with Parallel Computing”, Information Processing Letters, Vol. 114, No. 5, pp. 268-272, 2014.

  • M. Morales-Sandoval, C. Feregrino Uribe, P. Kitsos and R. Cumplido, “Area/Performance Trade-Off Analysis of an FPGA Digit-Serial Montgomery Multiplier based on LFSR”, Computers and Electrical Engineering, Vol. 39, No. 2, pp. 542-549, 2013.

  • P. Sakthivel, A. NirmalKumar and T. Mayilsamy, “Low Transition Test Pattern Generator Architecture for Built-in-Self-Test”, American Journal of Applied Sciences, Vol. 9, No. 9, pp. 1396-1406, 2012.

  • N. Mukherjee, J. Rajski, G. Mrugalski, A. Pogiel and J. Tyszer, “Ring Generator: An Ultimate Linear Feedback Shift Register”, Computer, Vol. 44, No. 6, pp. 64-71, 2011.

  • N. Concer, L. Bononi, M. Soulie, R. Locatelli and L. Carloni, “The Connection-Then-Credit Flow Control Protocol for Heterogeneous Multicore Systems-on-Chip”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 29, No. 6, pp. 869-882, 2010.

  • B. Zhou, Y. Ye, Z. Li, J. Zhang, X. Wu and R. Ke, “A Test Set Embedding Approach based on Twisted-Ring Counter with Few Seed”, Integration, the VLSI Journal, Vol. 43, No. 1, pp. 81-100, 2010.

  • A. Abu-Issa and S. Quigley, “Bit-Swapping LFSR and Scan-Chain Ordering: A Novel Technique for Peak- and Average-Power Reduction in Scan-Based BIST”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 28, No. 5, pp. 755-759, 2009.

  • Xinhui Zhang, C. Chen and A. Chakravarthy, “Structure Design and Optimization of 2-D LFSR-Based Multisequence Test Generator in Built-In Self-Test”, IEEE Transactions on Instrumentation and Measurement, Vol. 57, No. 3, pp. 651-663, 2008.

  • A. Abu-Issa and S. Quigley, “Bit-Swapping LFSR for Low-Power BIST”, Electronics Letters, Vol. 44, No. 6, pp. 401-403, 2008.

  • S. Wang, 2007. A BIST TPG for Low Power Dissipation and high Fault Coverage”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 15, No. 7, pp. 777-789, 2007.

  • J. Kakade and D. Kagaris, “Minimization of Linear Dependencies Through the Use of Phase Shifters”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 26, No. 10, pp. 1877-1882, 2007.

  • Z. Jiang, Y. Zhan, D. Chen and Y. Wang, “Two Methods of Directly Constructing Probabilistic Public-Key Encryption Primitives based on Third-Order LFSR Sequences”, Applied Mathematics and Computation, Vol. 171, No. 2, pp. 900-911, 2005.

  • P. Rosinger, B. Al-Hashimi and N. Nicolici, “Dual Multiple-Polynomial LFSR for Low-Power Mixed-Mode BIST”, IEEE Proceedings - Computers and Digital Techniques, Vol. 150, No. 4, pp. 209-217, 2003.

  • S. Wang and S. Gupta, “DS-LFSR: A BIST TPG for Low Switching Activity”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 21, No. 7, pp. 842-851, 2002.

  • D. Kagaris and S. Tragoudas, “Computational Analysis of Counter-based Schemes for VLSI Test Pattern Generation”, Discrete Applied Mathematics, Vol. 110, No. 2-3, pp. 227-250, 2001.

  • T. Sridhar, D. Ho, T. Powell and S. Thatte, “Analysis and Simulation of Parallel Signature Analyzers”, Computers and Mathematics with Applications, Vol. 13, No. 5-6, pp. 537-545, 1987.


Abstract Views: 199

PDF Views: 0




  • Broadband CPW Fed Polarization Reconfigurable Antenna for Universal UHF RFID Reader

Abstract Views: 199  |  PDF Views: 0

Authors

Sateesh Virothu
Department of Electronics and Communication Engineering, Andhra University College of Engineering, India
M. Satya Anuradha
Department of Electronics and Communication Engineering, Andhra University College of Engineering, India

Abstract


In this paper, a compact CPW fed polarization reconfigurable wideband antenna is presented for the application of a universal ultra-high frequency (UHF) radio frequency identification (RFID) antenna. In this work, long-range and random orientation detectability features are incorporated with the inclusion of polarization reconfigurability in the RFID reader antenna. Initially, a circularly polarized antenna is designed, which consists of a square slot embedded with an inverted L-shaped strip line and an F-shaped feeding structure, which is etched on the FR4_epoxy substrate. Secondly, the inclusion of three PIN diodes and an extra strip line connected to the feed structure are used to achieve linear as well as circular polarization. The desired performance is obtained in the whole UHF RFID frequency band (universally adopted range in the UHF band by the different countries) from 840 MHz to 960 MHz. Simulation, as well as experimentation procedures, are applied to obtain the details of the S11, gain, axial ratio, and radiation patterns. The experimented performance metrics are in good agreement with simulation results. The results reveal that axial ratio requirements for linear and circular polarizations are met in the required band of operation with accepTable.gain.

Keywords


RFID, Polarization Reconfigurable Antenna, CPW Feed, PIN Diodes, UHF Band.

References