ICTACT Journal on Microelectronics

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Design of Energy Efficient Approximate Multipliers for Image Processing Applications


Affiliations
1 Department of Electronics and Communication Engineering, Rao Bahadur Y Mahabaleswarappa Engineering College, India
2 Department of Electronics and Communication Engineering, Vemana Institute of Technology, India
     

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This research paper presents the design of two 8×8 approximate multipliers based on novel approximate 3:2 and 2:2 compressors. The proposed multipliers are derived based on Wallace multiplier architecture and herein referred to as the proposed ‘approximate Wallace multiplier’ (AWM). The performance of these proposed AWMs has been assessed and analyzed in terms of ‘Design Metrics’ (DMs) such as power, delay, ‘power-delay-product’ (PDP), and area. Further, a performance comparison of AWMs has been carried out against 6 other multipliers designed based on reported approximate 3:2 compressors. To extract these DMs, all the multipliers under consideration have been described using Verilog code and synthesized using Cadence’s ‘RTL Compiler’ (RC) tool using a 180 nm standard cell library. The synthesis results show that the proposed AWMs accomplish an excellent performance in terms of DMs. Further, the AWMs along with other designed Wallace multipliers, based on reported approximate compressors have been compared, under image processing application in terms of ‘peak signal-to-noise ratio’ (PSNR). The comparison results show that the proposed multipliers have a better PSNR (more than 50 dB).

Keywords

Approximate Computation, Wallace Multiplier, 3:2 Compressor, Low Power, PDP
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  • I. Alouani, H. Ahangari, O. Ozturk and S. Nair, “A Novel Heterogeneous Approximate Multiplier for Low Power and High Performance”, IEEE Embedded System Letters, Vol. 10, No. 2, pp. 45-48, 2018.

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  • M. Ostal, A. Ibrahim, H. Chible and M. Valle, “Inexact Arithmetic Circuits for Energy Efficient IoT Sensors Data Processing”, Proceedings of IEEE International Symposium on Circuits and Systems, pp. 1-4, 2018.

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  • A. Dalloo, A. Najafi and A. Garcia-Ortiz, “Systematic Design of an Approximate Adder: The Optimized Lower Part Constant-OR Adder”, IEEE Transactions on Very Large-Scale Integration (VLSI) Systems, Vol. 26, No. 8, pp. 1595-1599, 2018.

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  • Z. Yang, J. Han and F. Lombardi, “Approximate Compressors for Error-Resilient Multiplier Design”, Proceedings of IEEE International Conference on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, pp. 1-14, 2015.

  • G. Vaibhav, M. Debabrata, R. Anand and R. Kaushik, “Low-Power Digital Signal Processing using Approximate Adders”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 32, No. 1, pp. 124-137, 2013.

  • Z. Yang, A. Jain, J. Liang, J. Han and F. Lombardi, “Approximate XOR/XNOR-based Adders for Inexact Computing”, Proceedings of IEEE International Conference on Nanotechnology, pp. 690-693, 2013.

  • A.B. Kahng and S. Kang, “Accuracy-Configurable Adder for Approximate Arithmetic Designs”, Proceedings of IEEE International Conference on Design Auto, pp. 820-825, 2012.

  • D. Shin and S.K. Gupta, “Approximate Logic Synthesis for Error Tolerant Applications”, Proceedings of IEEE International Conference on Design, Automation, and Test, pp. 1-4, 2010.

  • H.R. Mahdiani, A. Ahmadi, S.M. Fakhraie and C. Lucas, “Bio-Inspired Imprecise Computational Blocks for Efficient VLSI Implementation of Soft-Computing Applications”, IEEE Transactions on Circuits and Systems-I: Regular Papers, Vol. 57, No. 4, pp. 850-862, 2010.

  • N. Zhu, W.L. Goh, W. Zhang, K.S. Yeo and Z.H. Kong, “Design of Low-Power High Speed Truncation-Error-Tolerant Adder and Its Application in Digital Signal Processing”, IEEE Transactions on Very Large-Scale Integration (VLSI) Systems, Vol. 18, No. 8, pp. 1225-1229, 2010.


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  • Design of Energy Efficient Approximate Multipliers for Image Processing Applications

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Authors

Chinna V. Gowdar
Department of Electronics and Communication Engineering, Rao Bahadur Y Mahabaleswarappa Engineering College, India
M. C. Parameshwara
Department of Electronics and Communication Engineering, Vemana Institute of Technology, India

Abstract


This research paper presents the design of two 8×8 approximate multipliers based on novel approximate 3:2 and 2:2 compressors. The proposed multipliers are derived based on Wallace multiplier architecture and herein referred to as the proposed ‘approximate Wallace multiplier’ (AWM). The performance of these proposed AWMs has been assessed and analyzed in terms of ‘Design Metrics’ (DMs) such as power, delay, ‘power-delay-product’ (PDP), and area. Further, a performance comparison of AWMs has been carried out against 6 other multipliers designed based on reported approximate 3:2 compressors. To extract these DMs, all the multipliers under consideration have been described using Verilog code and synthesized using Cadence’s ‘RTL Compiler’ (RC) tool using a 180 nm standard cell library. The synthesis results show that the proposed AWMs accomplish an excellent performance in terms of DMs. Further, the AWMs along with other designed Wallace multipliers, based on reported approximate compressors have been compared, under image processing application in terms of ‘peak signal-to-noise ratio’ (PSNR). The comparison results show that the proposed multipliers have a better PSNR (more than 50 dB).

Keywords


Approximate Computation, Wallace Multiplier, 3:2 Compressor, Low Power, PDP

References