ICTACT Journal on Microelectronics

Open Access Open Access  Restricted Access Subscription Access
Open Access Open Access Open Access  Restricted Access Restricted Access Subscription Access

Hardware Security Model With Vedic Multiplier Based Ecc Algorithm On High-performance Fpga Device


Affiliations
1 Department of Computer Science and Engineering, Bhilai Institute of Technology, India
     

   Subscribe/Renew Journal


The key problem that the world is most concerned about is security. Data security is the process of preventing unauthorized access to sensitive data. It includes all of the cybersecurity measures you take to keep your data safe from unauthorized access, such as encryption and access restrictions (both physical and digital). Data security has always been of the utmost importance. We utilize cryptographic methods to improve the services of data security. The application of cryptographic algorithms achieves data encryption. Therefore, we developed two versions of ECC algorithms on FPGA for improved hardware security in this study. The FPGA device employed here is Kintex-7, and there are two types of ECC: standard ECC and Vedic multiplier-based ECC. Vedic multiplier-based ECC has discovered that it consumes less space than standard ECC. Not only does Vedic multiplier-based ECC save space, but it also saves electricity. As a result, it is determined that for improved hardware security with ECC enabled, Vedic Multiplier-based ECC should be used over standard ECC.

Keywords

ECC, Vedic Multiplier based ECC, Area, Power, and FPGA
Subscription Login to verify subscription
User
Notifications
Font Size

  • Keshav Kumar, K.R. Ramkumar and Amanpreet Kaur, “A Lightweight AES Algorithm Implementation for Encrypting Voice Messages using Field Programmable Gate Arrays”, Journal of King Saud University-Computer and Information Sciences, Vol. 83, pp. 1-18, 2020.

  • Aryan Kaushik and Keshav Kumar, “Design and Implementation of Advanced Encryption Standard Algorithm on 7th Series Field Programmable Gate Array”, Proceedings of International Conference on Smart Structures and Systems, pp. 1-3, 2020.

  • Keshav Kumar, K.R. Ramkumar and Amanpreet Kaur, “A Design Implementation and Comparative Analysis of Advanced Encryption Standard (AES) Algorithm on FPGA”, Proceedings of International Conference on Reliability, Infocom Technologies and Optimization, pp. 182-185, 2020.

  • Keshav Kumar, K.R. Ramkumar and Amanpreet Kaur, “A Survey on Hardware Implementation of Cryptographic Algorithms Using Field Programmable Gate Array”, Proceedings of International Conference on Communication Systems and Network Technologies, pp. 189-194, 2020.

  • K. Kumar, S. Malhotra and A. Kumar, “Design of Thermal-Aware and Power-Efficient LFSR on Different Nanometer Technology FPGA for Green Communication”, Proceedings of International Conference on Communication Systems and Network Technologies, pp. 236-240, 2021.

  • K. Kumar, S. Malhotra and A. Kumar, 2019, "Frequency Scaling Based Low Power Oriya Unicode Reader (OUR) Design ON 40nm and 28nm FPGA”, International Journal of Recent Technology and Engineering, Vol. 7, No. 6, pp. 1-13, 2019.

  • Bishwajeet Pandey, Keshav Kumar and Aiza Batool Shabeer Ahmad, “Implementation of Power-Efficient Control Unit on Ultra-Scale FPGA for Green Communication”, 3C Tecnologia, Vol. 10, No. 1, pp. 93-105, 2021.

  • Bishwajeet Pandey and Keshav Kumar, “Leakage Power Consumption of Address Register Interfacing with Different Families of FPGA”, International Journal of InnovativeTechnology and Exploring Engineering, Vol. 9, No. 2, pp. 512-514, 2019.

  • Keshav Kumar, Amanpreet Kaur, S.N. Panda, “Effect of Different Nano Meter Technology Based FPGA on Energy Efficient UART Design”, Proceedings of International Conference on Communication Systems and Network Technologies, pp. 1-4, 2018.

  • C.T. Poomagal, G.A. Sathish Kumar and D. Mehta, “Revisiting the ECM-KEEM Protocol with Vedic Multiplier for Enhanced Speed on FPGA Platforms”, Journal of Ambient Intelligence and Humanized Computing, Vol. 98, pp. 1-11, 2021.

  • R.K. Kadu and D.S. Adane, “Hardware Implementation of Efficient Elliptic Curve Scalar Multiplication using Vedic Multiplier”, International Journal of Communication Networks and Information Security, Vol. 11, No. 2, pp. 270-277, 2019.

  • P. Ahuja, H. Soni and K. Bhavsar, “Fast, Secure and Efficient Vedic Approach for Cryptographic Implementations on FPGA”, Proceedings of International Conference on Electronics, Communication and Aerospace Technology, pp. 1706-1710, 2018.

  • P. Ahuja, H. Soni and K. Bhavsar, “High Performance Vedic Approach for Data Security using Elliptic Curve Cryptography on FPGA”, Proceedings of International Conference on Trends in Electronics and Informatics, pp. 187-192, 2018.

  • S. Karthikeyan and M. Jagadeeswari, “Performance Improvement of Elliptic Curve Cryptography System using Low Power, High Speed 16× 16 Vedic Multiplier based on Reversible Logic”, Journal of Ambient Intelligence and Humanized Computing, Vol. 12, No. 3, pp. 4161-4170, 2021.

  • R.K. Kodali, S.S. Yenamachintala and L. Boppana, “FPGA Implementation of 160-Bit Vedic Multiplier”, Proceedings of International Conference on Devices, Circuits and Communications, pp. 1-5, 2014.

  • T.S. Reddy and Y.D.S.Raju, “Implementation of Data Security with Wallace Tree Approach using Elliptical Curve Cryptography on FPGA”, Turkish Journal of Computer and Mathematics Education, Vol. 12, No. 6, pp. 1546-1553, 2021.


Abstract Views: 165

PDF Views: 0




  • Hardware Security Model With Vedic Multiplier Based Ecc Algorithm On High-performance Fpga Device

Abstract Views: 165  |  PDF Views: 0

Authors

Saurabh Singh
Department of Computer Science and Engineering, Bhilai Institute of Technology, India
Sunita Soni
Department of Computer Science and Engineering, Bhilai Institute of Technology, India

Abstract


The key problem that the world is most concerned about is security. Data security is the process of preventing unauthorized access to sensitive data. It includes all of the cybersecurity measures you take to keep your data safe from unauthorized access, such as encryption and access restrictions (both physical and digital). Data security has always been of the utmost importance. We utilize cryptographic methods to improve the services of data security. The application of cryptographic algorithms achieves data encryption. Therefore, we developed two versions of ECC algorithms on FPGA for improved hardware security in this study. The FPGA device employed here is Kintex-7, and there are two types of ECC: standard ECC and Vedic multiplier-based ECC. Vedic multiplier-based ECC has discovered that it consumes less space than standard ECC. Not only does Vedic multiplier-based ECC save space, but it also saves electricity. As a result, it is determined that for improved hardware security with ECC enabled, Vedic Multiplier-based ECC should be used over standard ECC.

Keywords


ECC, Vedic Multiplier based ECC, Area, Power, and FPGA

References