ICTACT Journal on Microelectronics

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Hardware Security Model With Vedic Multiplier Based Ecc Algorithm On High-performance Fpga Device


Affiliations
1 Department of Computer Science and Engineering, Bhilai Institute of Technology, India
     

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The key problem that the world is most concerned about is security. Data security is the process of preventing unauthorized access to sensitive data. It includes all of the cybersecurity measures you take to keep your data safe from unauthorized access, such as encryption and access restrictions (both physical and digital). Data security has always been of the utmost importance. We utilize cryptographic methods to improve the services of data security. The application of cryptographic algorithms achieves data encryption. Therefore, we developed two versions of ECC algorithms on FPGA for improved hardware security in this study. The FPGA device employed here is Kintex-7, and there are two types of ECC: standard ECC and Vedic multiplier-based ECC. Vedic multiplier-based ECC has discovered that it consumes less space than standard ECC. Not only does Vedic multiplier-based ECC save space, but it also saves electricity. As a result, it is determined that for improved hardware security with ECC enabled, Vedic Multiplier-based ECC should be used over standard ECC.

Keywords

ECC, Vedic Multiplier based ECC, Area, Power, and FPGA
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  • P. Ahuja, H. Soni and K. Bhavsar, “Fast, Secure and Efficient Vedic Approach for Cryptographic Implementations on FPGA”, Proceedings of International Conference on Electronics, Communication and Aerospace Technology, pp. 1706-1710, 2018.

  • P. Ahuja, H. Soni and K. Bhavsar, “High Performance Vedic Approach for Data Security using Elliptic Curve Cryptography on FPGA”, Proceedings of International Conference on Trends in Electronics and Informatics, pp. 187-192, 2018.

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  • Hardware Security Model With Vedic Multiplier Based Ecc Algorithm On High-performance Fpga Device

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Authors

Saurabh Singh
Department of Computer Science and Engineering, Bhilai Institute of Technology, India
Sunita Soni
Department of Computer Science and Engineering, Bhilai Institute of Technology, India

Abstract


The key problem that the world is most concerned about is security. Data security is the process of preventing unauthorized access to sensitive data. It includes all of the cybersecurity measures you take to keep your data safe from unauthorized access, such as encryption and access restrictions (both physical and digital). Data security has always been of the utmost importance. We utilize cryptographic methods to improve the services of data security. The application of cryptographic algorithms achieves data encryption. Therefore, we developed two versions of ECC algorithms on FPGA for improved hardware security in this study. The FPGA device employed here is Kintex-7, and there are two types of ECC: standard ECC and Vedic multiplier-based ECC. Vedic multiplier-based ECC has discovered that it consumes less space than standard ECC. Not only does Vedic multiplier-based ECC save space, but it also saves electricity. As a result, it is determined that for improved hardware security with ECC enabled, Vedic Multiplier-based ECC should be used over standard ECC.

Keywords


ECC, Vedic Multiplier based ECC, Area, Power, and FPGA

References