Open Access Open Access  Restricted Access Subscription Access
Open Access Open Access Open Access  Restricted Access Restricted Access Subscription Access

DESIGN OF NOISE TOLERANCE 9T SRAM CELL


Affiliations
1 Department of Electronics and Communication Engineering, Madanapalle Institute of Technology and Science., India
     

   Subscribe/Renew Journal


This paper describes the well-thought-out design of a 9T Static Random Access Memory single Bit cell with enhanced performance. MonteCarlo simulations are utilized for this proposed 9T SRAM circuit, and the outcomes are verified by comparing with various like Conv6T, Conv7T and Conv8T SRAM cells in the 22-nm PTM with variable supply voltage. The proposed 9T SRAM shows 1.02/1.265/ 0.259 × lesser read delay and 1.028/1.032/0.857 × write delay as compared to Conv6T/Conv7T/ Conv8T respectively. Our proposed 9T SRAM showing 2.06/12.5 × less leakage power dissipation as compared to Conv6T/ Conv8T respectively.

Keywords

Read Access Time, Write Access Time, Read SNM, Read Power, Write Power, Hold Power
Subscription Login to verify subscription
User
Notifications
Font Size


  • DESIGN OF NOISE TOLERANCE 9T SRAM CELL

Abstract Views: 424  |  PDF Views: 0

Authors

Chandramuleswar Roy
Department of Electronics and Communication Engineering, Madanapalle Institute of Technology and Science., India
Naveen
Department of Electronics and Communication Engineering, Madanapalle Institute of Technology and Science., India
Jaswanth Achari
Department of Electronics and Communication Engineering, Madanapalle Institute of Technology and Science., India
Naresh K. Reddy
Department of Electronics and Communication Engineering, Madanapalle Institute of Technology and Science., India

Abstract


This paper describes the well-thought-out design of a 9T Static Random Access Memory single Bit cell with enhanced performance. MonteCarlo simulations are utilized for this proposed 9T SRAM circuit, and the outcomes are verified by comparing with various like Conv6T, Conv7T and Conv8T SRAM cells in the 22-nm PTM with variable supply voltage. The proposed 9T SRAM shows 1.02/1.265/ 0.259 × lesser read delay and 1.028/1.032/0.857 × write delay as compared to Conv6T/Conv7T/ Conv8T respectively. Our proposed 9T SRAM showing 2.06/12.5 × less leakage power dissipation as compared to Conv6T/ Conv8T respectively.

Keywords


Read Access Time, Write Access Time, Read SNM, Read Power, Write Power, Hold Power

References