ICTACT Journal on Microelectronics

Open Access Open Access  Restricted Access Subscription Access
Open Access Open Access Open Access  Restricted Access Restricted Access Subscription Access

DESIGN OF NOISE TOLERANCE 9T SRAM CELL


Affiliations
1 Department of Electronics and Communication Engineering, Madanapalle Institute of Technology and Science., India
     

   Subscribe/Renew Journal


This paper describes the well-thought-out design of a 9T Static Random Access Memory single Bit cell with enhanced performance. MonteCarlo simulations are utilized for this proposed 9T SRAM circuit, and the outcomes are verified by comparing with various like Conv6T, Conv7T and Conv8T SRAM cells in the 22-nm PTM with variable supply voltage. The proposed 9T SRAM shows 1.02/1.265/ 0.259 × lesser read delay and 1.028/1.032/0.857 × write delay as compared to Conv6T/Conv7T/ Conv8T respectively. Our proposed 9T SRAM showing 2.06/12.5 × less leakage power dissipation as compared to Conv6T/ Conv8T respectively.

Keywords

Read Access Time, Write Access Time, Read SNM, Read Power, Write Power, Hold Power
Subscription Login to verify subscription
User
Notifications
Font Size

  • D.H. Lee, D.K. Kwak and K.S. Min, “Comparative Study on SRAMs for Suppressing Both Oxide-Tunneling Leakage and Subthreshold Leakage in Sub-70-nm Leakage Dominant VLSIs”, Proceedings of International Conference on VLSI Design Held Jointly International Conference on Embedded Systems, pp. 632-637, 2007.

  • C. Roy and A. Islam, “Power-Aware Source Feedback Single-Ended 7T SRAM Cell at Nanoscale Regime”, Microsystem Technology, Vol. 25, pp. 1783-1791, 2019.

  • V.K. Mishra, N. Yadava and R.K. Chauhan, “Analysis of RSNM and WSNM of 6T SRAM Cell Using Ultra Thin Body FD-SOI MOSFET”, Proceedings of International Conference on Advances in Signal Processing and Communication, pp. 1-13, 2019.

  • N. Yadav, S. Khandelwal and S. Akashe, “Design and Analysis of FINFET Pass Transistor based XOR and XNOR Circuits at 45 nm Technology”, Proceedings of International Conference on Control, Computing, Communication and Materials, pp. 1-5, 2013.

  • T. Raja, V.D. Agrawal and M.L. Bushnell, “Variable Input Delay CMOS Logic for Low Power Design”, Proceedings of International Conference on VLSI Design, pp. 598-605, 2005.

  • A. Sinha and A. Islam, “Low-Power Half-Select Free Single-Ended 10 Transistor SRAM Cell”, Microsystem Technology, Vol. 23, pp. 4133-4144, 2017.

  • D. Lee and K. Roy, “Area Efficient ROM-Embedded SRAM Cache”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 21, No. 9, pp. 1583-1595, 2013.

  • M. Kavitha and T. Govindaraj, “Low-Power Multimodal Switch for Leakage Reduction and Stability Improvement in SRAM Cell”, Arabian Journal for Science and Engineering, Vol. 41, pp. 2945-2955, 2016.

  • S. Cheng and S. Huang, “A Low-Power SRAM for Viterbi Decoder in Wireless Communication”, IEEE Transactions on Consumer Electronics, Vol. 54, No. 2, pp. 290-295, 2008.

  • C. Roy and A. Islam, “Characterization of Single-Ended 9T SRAM Cell”, Microsystem Technology, Vol. 26, pp. 1591- 1604, 2020.

  • C. Roy and A. Islam, “Design of Differential TG based 8T SRAM Cell for Ultralow-Power Applications”, Microsystem Technology, Vol. 26, pp. 3299-3310, 2020.

  • Chandramauleshwar Roy and Aminul Islam, “Design of Low Power, Variation Tolerant Single Bitline 9T SRAM Cell in 16-nm Technology in Subthreshold Region”, Microelectronics Reliability, Vol. 120, pp. 114-126, 2021.

  • Aminul Islam, Mohd. Hasan and Tughrul Arslan, “Variation Resilient Subthreshold SRAM Cell Design Technique”, International Journal of Electronics, Vol. 99, No. 9, pp. 1223-1237, 2012.

  • N. Anand, A. Sinha, C. Roy and A. Islam, “Design of a Stable Read-Decoupled 6T SRAM Cell at 16-Nm Technology Node”, Proceedings of International Conference on Computational Intelligence and Communication Technology, pp. 524-528, 2015.

  • C. Roy and A. Islam, “Comparative Analysis of Various 9T SRAM Cell at 22-nm Technology Node”, Proceedings of International Conference on Recent Trends in Information Systems, pp. 491-496, 2015.

  • K. Dnyaneshwar and L.V. Birgale, “Power Optimization in 8T SRAM Cell”, Proceedings of International Conference ISSN: 2395-1680 (ONLINE) ICTACT JOURNAL ON MICROELECTRONICS, JULY 2022, VOLUME: 08, ISSUE: 02 1349 on Computing Communication Control and Automation, pp. 11-15, 2016.

  • B.S. Kariyappa and A. Namitha Palecha, “A Comparative Study of 7T SRAM Cells”, International Journal of Computer Trends and Technology, Vol. 4, No. 7, pp. 2188- 2191, 2013.

  • M. Qazi., M.E. Sinangil and A.P. Chandrakasan, “Challenges and Directions for Low-Voltage SRAM”, Design and Test of Computers, Vol. 28, No. 1, pp. 32-43, 2011.

  • H. Noguchi, “Which is the best Dual-Port SRAM in 45-nm Process Technology? - 8T, 10T Single End, and 10T Differential”, Proceedings of International Conference on Integrated Circuit Design and Technology, pp. 55-58, 2008.

  • A. Feki, B Allard, D. Turgis, J. Lafont and L. Ciampolini, “Proposal of a New Ultra Low Leakage 10T Sub Threshold SRAM Bitcell”, Proceedings of International Conference on SoC, pp. 470-474, 2012.

  • A. Islam and M. Hasan, “Leakage Characterization of 10T SRAM Cell”, IEEE Transactions on Electron Devices, Vol. 59, No. 3, pp. 631-638, 2012.

  • Adam Teman, Omer Cohen and Alexander Fish, “A 250 mV 8 kb 40 nm Ultra-Low Power 9T Supply Feedback SRAM (SF-SRAM)”, IEEE Journal of Solid-State Circuits, Vol. 46, No. 11, pp. 1-13, 2011.

  • Bo Wang, “Design of an Ultra-Low Voltage 9T SRAM with Equalized Bitline Leakage and CAM-Assisted Energy Efficiency Improvement”, IEEE Transactions on Circuits Systems I, Vol. 23, No. 2, pp. 1-14, 2014


Abstract Views: 303

PDF Views: 0




  • DESIGN OF NOISE TOLERANCE 9T SRAM CELL

Abstract Views: 303  |  PDF Views: 0

Authors

Chandramuleswar Roy
Department of Electronics and Communication Engineering, Madanapalle Institute of Technology and Science., India
Naveen
Department of Electronics and Communication Engineering, Madanapalle Institute of Technology and Science., India
Jaswanth Achari
Department of Electronics and Communication Engineering, Madanapalle Institute of Technology and Science., India
Naresh K. Reddy
Department of Electronics and Communication Engineering, Madanapalle Institute of Technology and Science., India

Abstract


This paper describes the well-thought-out design of a 9T Static Random Access Memory single Bit cell with enhanced performance. MonteCarlo simulations are utilized for this proposed 9T SRAM circuit, and the outcomes are verified by comparing with various like Conv6T, Conv7T and Conv8T SRAM cells in the 22-nm PTM with variable supply voltage. The proposed 9T SRAM shows 1.02/1.265/ 0.259 × lesser read delay and 1.028/1.032/0.857 × write delay as compared to Conv6T/Conv7T/ Conv8T respectively. Our proposed 9T SRAM showing 2.06/12.5 × less leakage power dissipation as compared to Conv6T/ Conv8T respectively.

Keywords


Read Access Time, Write Access Time, Read SNM, Read Power, Write Power, Hold Power

References