100MHZ-2GHZ PULSE TRIGGERED FLIP-FLOPS IN 32NM TECHNOLOGY FOR LOW POWER AND HIGH PERFORMANCE DIGITAL CMOS CIRCUITS

This study presents extensive work carried out on pulse triggered flip flops (P-FFs) for power consumption, area requirements and delay measurements. Six latest state-of-art P-FFs are used to determine these performance parameters. The flip flops are Conditional Pulse Enhancement P-FF (CPEPFF), Signal Feed-through P-FF (SFTPFF) Karimi’s P-FF (KPFF), Conditional Feed-through P-FF (CFTPFF), Dual Dynamic node hybrid FF (DDFF), and Dual-edge Implicit FF with an embedded Clock Gated Scheme (DIFF-CGS). Simulations are carried out at 32nm CMOS technology on T-SPICE at operating conditions of 500MHz clock frequency, temperature of 25°C with 50% data activity. Results showed that CFTPFF consumes the least average power with minimum reduction of 27.94% and maximum of 57.45%. Even at higher frequencies and varying data activities CFTPFF outperforms other FFs in power dissipation. DDFF is the fastest P-FF with minimum enhancements of 82.7% and maximum 94%. In terms of power delay product (PDP), the optimal PDP of DDFF is best among all the P-FFs whereas DIFF-CGS has the worst. The area overhead of KPFF and CFTPFF is better compared to the rest of P-FFs.