ICTACT Journal on Microelectronics

Open Access Open Access  Restricted Access Subscription Access
Open Access Open Access Open Access  Restricted Access Restricted Access Subscription Access

Low Power Dynamic Cmos Inverter And Sram Cell Design Using Lector And Lector-B Technique


Affiliations
1 Department of Electronics and Communication Engineering, India
2 Department of Electronics and Communication Engineering, Sant Longowal Institute of Engineering and Technology, India
3 Department of Electronics and Communication Engineering, Dr. B.R. Ambedkar National Institute of Technology, India
     

   Subscribe/Renew Journal


At the current deep submicron and nanometer level, the leakage power is becoming the major contributor to overall power consumption in modern VLSI circuits. This research paper presents a novel approach to reducing leakage power by inserting two leakage transistors in the middle of pull-down and pull-up paths. Out of these two leakage transistors, one is the PMOS transistor, and another one is the NMOS transistor. This research work presents a dynamic CMOS inverter and 6T SRAM cell with and without transmission gate (TG) to reduce leakage power using the LECTOR and LECTOR-B techniques. The Cadence Virtuoso simulation tool is used to presents the results in terms of static power. Using the 45-nm technology node, the performance in terms of static power is analyzed. It is observed that using LECTOR and LECTOR-B techniques, the overall reduction in static power is 26% and 20%, respectively, compared to the conventional design for SRAM cell. Similar improvements are also noted for dynamic CMOS inverter and TG SRAM cell.

Keywords

Dynamic CMOS Inverter, SRAM Cell, Leakage Power, LECTOR, LECTOR-B Technique
Subscription Login to verify subscription
User
Notifications
Font Size

  • A. Agarwal, S. Mukhopadhyay, A. Raychowdhury, K. Roy and C.H. Kim, “Leakage Power Analysis and Reduction for Nanoscale Circuits”, IEEE Micro, Vol. 26, No. 2, pp. 68-80, 2006.

  • Jian Hong Yang, Gui Fang Li and Hui Lan Liu, “Off-State Leakage Current in Nano-Scale MOSFET with Hf-based Gate Dielectrics”, Proceedings of IEEE International Conference on Nanoelectronics, pp. 1189-1192, 2008.

  • K. Roy, S. Mukhopadhyay and H. Mahmoodi-Meimand, “Leakage Current Mechanisms and Leakage Reduction Techniques in Deep-Submicrometer CMOS Circuits”, Proceedings of IEEE, Vol. 91, No. 2, pp. 305-327, 2003.

  • Dongwoo Lee, D. Blaauw and D. Sylvester, “Gate Oxide Leakage Current Analysis and Reduction for VLSI Circuits”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 12, No. 2, pp. 155-166, 2004.

  • A.P. Shah, V. Neema and S. Daulatabad, “Effect of Process, Voltage and Temperature (PVT) Variations In LECTOR-B (Leakage Reduction Technique) at 70 nm Technology Node”, Proceedings of IEEE International Conference on Computer, Communication and Control, pp. 1-6, 2015.

  • N. Hanchate and N. Ranganathan, “LECTOR: A Technique for Leakage Reduction in CMOS Circuits”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 12, No. 2, pp. 196-205, 2004.

  • M. Leela, S. Rooban and C. Joshitha, “Comparative Analysis on Low Power SRAMs”, Materials Today Proceedings, Vol. 23, No. 2, pp. 1-13, 2020.

  • P. Verma and R.A. Mishra, “Leakage Power and Delay Analysis of LECTOR based CMOS Circuits”, Proceedings of International Conference on Computer and Communication Technology, pp. 260-264, 2011.

  • M.C. Johnson, D. Somasekhar, Lih Yih Chiou and K. Roy, “Leakage Control with Efficient Use of Transistor Stacks in Single Threshold CMOS”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 10, No. 1, pp. 1-5, 2002.

  • R. Giterman, M. Vicentowski, I. Levi, Y. Weizman, O. Keren and A. Fish, “Leakage Power Attack-Resilient Symmetrical 8T SRAM Cell”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 26, No. 10, pp. 2180-2184, 2018.

  • B. Kankanala, A. Srinivasulu and S. Musala, “7-T Single End and 8-T Differential Dual-Port SRAM Memory Cells”, Proceedings of IEEE International Conference on Information and Communication Technologies, pp. 12431246, 2013.

  • R. Gupta, S.S. Gill and N. Kaur, “A Novel Low Leakage and High Density 5T CMOS SRAM Cell in 45nm Technology”, Proceedings of IEEE International Conference on Recent Advances in Engineering and Computational Sciences, pp. 1-6, 2014.

  • N. Yadav, S. Dutt and G.K. Sharma, “A New SensitivityDriven Process Variation Aware Self-Repairing Low-Power SRAM Design”, Proceedings of IEEE International Conference on VLSI Design, pp. 116-121, 2014.

  • J.M. Rabaey, A. Chandrakasan and Nikolic Borivoje, “Digital Integrated Circuits”, 2nd Edition, Pearson Education, 2003.

  • S.M. Kang, C.W. Kim and Y. Leblebici, “CMOS Digital Integrated Circuits Analysis and Design”, 4th Edition, McGraw-Hill India, 2019.

  • T.K. Gupta and K. Khare, “Lector with Footed-Diode Inverter: A Technique for Leakage Reduction in Domino Circuits”, Circuits, Systems, and Signal Processing, Vol. 32, No. 6, pp. 2707-2722, 2013.

  • G. Pasandi and S.M. Fakhraie, “A 256-kb 9T NearThreshold SRAM With 1k Cells per Bitline and Enhanced Write and Read Operations”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 23, No. 11, pp. 2438-2446, 2015.

  • V.S. Baghel and S. Akashe, “Low Power Memristor based 7T SRAM using MTCMOS Technique”, Proceedings of IEEE International Conference on Advance Computing and Communication Technology, pp. 222-226, 2015.Conference on Advances in Electrical, Electronics, Information, Communication and Bio-Informatics, pp. 351-357, 2016

  • C.A. Kumar, B.K. Madhavi and K. Lalkishore, “Performance Analysis of Low Power 6T SRAM Cell in 180nm and 90nm”, Proceedings of IEEE International


Abstract Views: 120

PDF Views: 0




  • Low Power Dynamic Cmos Inverter And Sram Cell Design Using Lector And Lector-B Technique

Abstract Views: 120  |  PDF Views: 0

Authors

Vivek Harshey
Department of Electronics and Communication Engineering, India
Pankaj Kumar Das
Department of Electronics and Communication Engineering, Sant Longowal Institute of Engineering and Technology, India
Shivani Sharma
Department of Electronics and Communication Engineering, Dr. B.R. Ambedkar National Institute of Technology, India

Abstract


At the current deep submicron and nanometer level, the leakage power is becoming the major contributor to overall power consumption in modern VLSI circuits. This research paper presents a novel approach to reducing leakage power by inserting two leakage transistors in the middle of pull-down and pull-up paths. Out of these two leakage transistors, one is the PMOS transistor, and another one is the NMOS transistor. This research work presents a dynamic CMOS inverter and 6T SRAM cell with and without transmission gate (TG) to reduce leakage power using the LECTOR and LECTOR-B techniques. The Cadence Virtuoso simulation tool is used to presents the results in terms of static power. Using the 45-nm technology node, the performance in terms of static power is analyzed. It is observed that using LECTOR and LECTOR-B techniques, the overall reduction in static power is 26% and 20%, respectively, compared to the conventional design for SRAM cell. Similar improvements are also noted for dynamic CMOS inverter and TG SRAM cell.

Keywords


Dynamic CMOS Inverter, SRAM Cell, Leakage Power, LECTOR, LECTOR-B Technique

References