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An Analysis to Design Merged Delay Transformed Iir down Sampler Filter:An Efficient down Sampler Filter Architecture


Affiliations
1 Department of Electrical Engineering, Modi Institute of Technology, India
2 Department of Electronics and Communication Engineering, Rajasthan Technical University, India
     

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An efficient architecture of Down Sampler Filter using Merged Delay Transformed Technique in terms of cost reduction and increase throughput has been proposed. The stability analysis of Merged Delay Transformed filters, finite word length effect on Transformed filters as well as conventional filters and peak error between the output from transformed IIR filters and from conventional filters have been investigated on the basis of commercially available software and mathematical calculations. The Butterworth, Chebyshev-1, Chebyshev-2 and Elliptic filters have been considered in this paper for the sake of comparison. The simulation results show that 84.59%, 73.56% and 50.83%&78.71%, 73.85% and 51.89% reduction in cost can be achieved with different specifications by using the proposed scheme when it is compared with conventional FIR filter, conventional IIR filter and conventional polyphase IIR filter, respectively. It has been elaborated that the stability of transformed IIR Decimation filters will not disturb as the Decimation Factor M increases. It is also shown that the transformed Elliptic filter is more stable and the transformed Chebyshev-2 filter is a marginally stable filter. The simulation results show that the peak error is in the range of 10-10 to 10-17 which increases with an increase in order of the filter. On the basis of simulation results and mathematical calculations, it is shown that the decomposition of higher order system into 1st order and 2nd order systems using parallel implementation architecture with Merged Delay Transform increases the processing rate of the filter and a reduction in the cost of implementation as well as peak error.

Keywords

Finite Word Length Effect, IIR Down Sampler Filter, Merged Delay Transformation, Stability.
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  • Matti Karjalainen, Tuomas Paatero, Jyri Pakarinen and Vesa Välimäki, “Special Digital Filters for Audio Reproduction”, Proceedings of 32nd International AES Conference, pp. 1-18, 2007.

  • William J. Randel, “Filtering and Data Preprocessing for Time Series”, Statistical Methods for Physical Science, Series: Methods of Experimental Physics, Vol. 28, pp. 283-311, 1994.

  • Mahesh S. Chavan, Ra Agarwala and M. D. Uplane, “Digital Elliptic Filter Application for Noise Reduction in ECG Signal”, Proceedings of 4th WSEAS International Conference on Electronics, Control and Signal Processing, Vol. 3, No. 1, pp. 58-63, 2005.

  • Chi-Jui Chou, Satish Mohanakrishnan and Joseph B. Evans, “FPGA Implementation of Digital Filters”, Proceedings of 4th International Conference on Signal Processing Applications and Technology, pp. 1-9, 1993.

  • A. Fernandez-Vazquez and Gordana Jovanovic-Dolecek, “A New Method for the Design of IIR Filters with Flat Magnitude Response”, IEEE Transactions on Circuits and Systems-I: Regular Papers, Vol. 53, No. 8, pp. 1761-1771, 2006.

  • K. Surma-Aho and T. Saramaki, “A Systematic Technique for Designing Approximately Linear Phase Recursive Digital Filters”, IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing, Vol. 46, No. 7, pp. 956-963, 1999.

  • Alan V. Oppenheim, Ronald W. Schafer and John R. Buck, “Discrete-Time Signal Processing”, 2nd Edition, Prentice Hall, 1999.

  • Andrew I. Russell, “Efficient Rational Sampling Rate Alteration using IIR Filters”, IEEE Signal Processing Letters, Vol. 7, No. 1, pp. 6-7, 2000.

  • Geoffrey A. Williamson, “Adaptive IIR Filters”, Digital Signal Processing Handbook, 1999.

  • David A. Johns and David M. Lewis, “Design and Analysis of Delta-Sigma Based IIR Filter”, IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing, Vol. 40, No. 4, pp. 233-240, 1993.

  • S.C. Chan, K.M. Tsui and K.W. Tse, “Design of Constrained Causal Stable IIR Filters Using a New Second-Order-Cone-Programming-Based Model-Reduction Technique”, IEEE Transactions on Circuits and Systems-II: Express Briefs, Vol. 54, No. 2, pp. 107-111, 2007.

  • J.G. Chung and K.K. Parhi, “Design of Pipelined Lattice IIR Digital Filters”, Proceedings of the 25th Asilomar Conference on Signals, Systems and Computers, Vol. 2, pp. 1021-1025, 1991.

  • Yong Ching Lim, “Frequency-Response Masking Approach for the Synthesis of Sharp Linear Phase Digital Filters”, IEEE Transactions on Circuits and Systems, Vol. 33, No. 4, pp. 357-364, 1986.

  • T. Saramaki and J. Yli-Kaakinen, “A Novel Systematic Approach for Synthesizing Multiplication-Free Highly-Selective FIR Half-Band Decimators and Interpolators” Proceedings of IEEE Asia Pacific Conference Circuits and Systems, pp. 920-923, 2006.

  • Z.P. Ma and Bosco Leung, “Polyphase IIR Decimation Filter Design for Oversampled A/D Converters with Approximately Linear Phase”, IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing, Vol. 39, No. 8, pp. 497-505, 1992.

  • Rozita Teymourzadeh and Masuri Othman Bin, “An Enhancement of Decimation Process using Fast Cascaded Integrator Comb (CIC) Filter”, Proceedings of IEEE International Conference on Semiconductor Electronics, pp. 811-815. 2006.

  • Alan.V. Oppenheim and Ronald. W. Schafer, “Digital Signal Processing”, Prentice-Hall, 1975

  • Giovanni Bianchi and Roberto Sorrentino, “Electronic Filter Simulation & Design”, McGraw-Hill, 2007.

  • Sajjan Godara, Nitesh Goyal and M.S. Pattar, “Efficient Digital Decimation Filter Designs for Improved Frequency Response in High Frequency Applications”, Proceedings of National Conference on Advances in Engineering and Technology, pp. 38-42, 2014.

  • Umar Farooq, “Efficient Architectural Transformation of Multirate Recursive Filters”, Ph. D Thesis, Department of Electrical Engineering, University of Engineering and Technology, Taxila, Pakistan, 2008.

  • Umar Farooq, Habibullah Jamal, and Shoab Ahmed Khan, “Realization of IIR Decimation Filters based on Merged Delay Transformation”, Research Letters in Signal Processing, Vol. 2007, pp. 1-3, 2007.

  • Suraj R. Gaikwad and Gopal Gawande, “Design of Highly Efficient Multirate Digital Filters”, International Journal of Engineering Research and Applications, Vol. 3, No. 6, pp. 560-564, 2013.

  • U. Rashid, F. Siddiq, T. Muhammad and H. Jamal, “Area Efficient Decimation Filter Based on Merged Delay Transformation for Wireless Applications”, The Nucleus, Vol. 45, No. 4, pp. 301-310, 2013.

  • A. Patni and V. Soni, “Merged Delay Transformed IIR Down Sampler Filter: An Efficient Architecture and Cost Reduction Technique for Implementation”, Proceedings of International Conference on Industrial Instrumentation and Control, pp. 159-164, 2015.

  • Stelios Kotsios, “A Note on BIBO Stability of Bilinear Systems”, Journal of the Franklin Institute, Vol. 332, No. 6, pp. 755 - 760, 1995.

  • Wu-Sheng Lu, “Design of Recursive Digital Filters with Prescribed Stability Margin: A Parameterization Approach”, IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing, Vol. 45, No. 9, pp. 1289-1298, 1998.

  • B.W. Bomar, “Finite Wordlength Effects”, Digital Signal Processing Handbook, 1999.

  • A. Patni & V. Soni, “Stability Analysis and Finite Word Length Effect on Merged Delay Transformed IIR Down Sampler Filters”, Proceedings of International Conference on Communications and Signal Processing, pp. 89-94, 2015.


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  • An Analysis to Design Merged Delay Transformed Iir down Sampler Filter:An Efficient down Sampler Filter Architecture

Abstract Views: 394  |  PDF Views: 0

Authors

V. Soni
Department of Electrical Engineering, Modi Institute of Technology, India
G. Parmar
Department of Electronics and Communication Engineering, Rajasthan Technical University, India

Abstract


An efficient architecture of Down Sampler Filter using Merged Delay Transformed Technique in terms of cost reduction and increase throughput has been proposed. The stability analysis of Merged Delay Transformed filters, finite word length effect on Transformed filters as well as conventional filters and peak error between the output from transformed IIR filters and from conventional filters have been investigated on the basis of commercially available software and mathematical calculations. The Butterworth, Chebyshev-1, Chebyshev-2 and Elliptic filters have been considered in this paper for the sake of comparison. The simulation results show that 84.59%, 73.56% and 50.83%&78.71%, 73.85% and 51.89% reduction in cost can be achieved with different specifications by using the proposed scheme when it is compared with conventional FIR filter, conventional IIR filter and conventional polyphase IIR filter, respectively. It has been elaborated that the stability of transformed IIR Decimation filters will not disturb as the Decimation Factor M increases. It is also shown that the transformed Elliptic filter is more stable and the transformed Chebyshev-2 filter is a marginally stable filter. The simulation results show that the peak error is in the range of 10-10 to 10-17 which increases with an increase in order of the filter. On the basis of simulation results and mathematical calculations, it is shown that the decomposition of higher order system into 1st order and 2nd order systems using parallel implementation architecture with Merged Delay Transform increases the processing rate of the filter and a reduction in the cost of implementation as well as peak error.

Keywords


Finite Word Length Effect, IIR Down Sampler Filter, Merged Delay Transformation, Stability.

References