Table of Contents
Vol 1, No 3 (2015)
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Articles
Gate Engineering of Double Gate In0.53Ga0.47As Tunnel FET | ||
C. S. Praveen, Ajith Ravindran, Shajimon K. John, Susan Abe | ||
Vol 1, No 3 (2015), Pagination: 91-95 | ||
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Abstract Views: 246 | PDF Views: 0 |
Behavioral Modelling of CMOSFETs and CNTFETs Based Low Noise Amplifier | ||
Navaid Z. Rizvi, Rajesh Mishra, Prashant Gupta | ||
Vol 1, No 3 (2015), Pagination: 96-100 | ||
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Abstract Views: 277 | PDF Views: 0 |
An Analysis to Design Merged Delay Transformed Iir down Sampler Filter:An Efficient down Sampler Filter Architecture | ||
V. Soni, G. Parmar | ||
Vol 1, No 3 (2015), Pagination: 101-114 | ||
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Abstract Views: 351 | PDF Views: 0 |
High Speed Online Fault Detection of 64-Bit Ripple Carry Adder Using Modified Modular Redundancy | ||
Jisha M. Nair, C. Pradeep | ||
Vol 1, No 3 (2015), Pagination: 115-119 | ||
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Abstract Views: 237 | PDF Views: 0 |
Case Study of Explicit and Implicit Pulsed Flip Flops with Conditional Pulse Enhancement Mechanism | ||
Thara Sebastian, A. Aravindhan | ||
Vol 1, No 3 (2015), Pagination: 120-123 | ||
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Abstract Views: 261 | PDF Views: 0 |
Analytical Modelling of Low Pressure Single Boss Sculptured Diaphragm and its Sensitivity Enhancement | ||
D. Sindhanaiselvi, R. Ananda Natarajan, T. Shanmuganantham | ||
Vol 1, No 3 (2015), Pagination: 124-130 | ||
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Abstract Views: 332 | PDF Views: 20 |
Pattern and Position Dependent Gate Leakage and Reduction Technique | ||
K. S. Sreekala, S. Krishna Kumar | ||
Vol 1, No 3 (2015), Pagination: 131-135 | ||
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Abstract Views: 237 | PDF Views: 0 |