ICTACT Journal on Microelectronics

Open Access Open Access  Restricted Access Subscription Access
Open Access Open Access Open Access  Restricted Access Restricted Access Subscription Access

High Speed Online Fault Detection of 64-Bit Ripple Carry Adder Using Modified Modular Redundancy


Affiliations
1 Department of Electronics and Communication Engineering, Saintgits College of Engineering, India
     

   Subscribe/Renew Journal


Developments in VLSI technology has increased density of chips so that, processing elements are capable of doing complex computations. The increase in complexity and density of the VLSI chip has made electronic systems more susceptible to defects. Therefore, testing and fault tolerance techniques are required to guarantee reliable operations of systems. Online fault detection techniques are active during normal operations. This paper proposes a novel online fault detection technique for 64-bit Ripple Carry Adder based on type of input data. A technique is developed to detect the single stuck-at faults that occur in the Ripple Carry Adder by using two rail checker. The design was modeled using Verilog HDL and simulated and synthesized in Xilinx ISE 14.5. A comparison is made by implementing the design in different FPGA devices. The results show that the proposed design has better device utilization and less delay in Virtex 5 FPGA. The proposed technique has only 16.2% delay overhead compared to simple Ripple Carry Adder without fault detection.

Keywords

Defect, Fault, FPGA, Online Fault Detection, Two Rail Checker.
Subscription Login to verify subscription
User
Notifications
Font Size

  • M. Bushnell and Vishwani Agrawal, “Essential of Electronic Testing for Digital, Memory and Mixed Signal VLSI Circuits”, Springer, pp. 60-80, 225,234, 2002.

  • D.P. Vasudevan, P.K. Lala and J.P. Parkerson, “Self-Checking Carry-Select Adder Design based on Two-Rail Encoding”, IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 54, No. 12, pp. 2696-2705, 2007.

  • E. Stott, P. Sedcole and P.Y.K. Cheung, “Fault Tolerant Methods for Reliability in FPGAs”, Proceedings of International Conference on Field Programmable Logic and Applications, pp. 415-420, 2008.

  • R.E. Lyons and W. Vanderkulk, “The Use of Triple-Modular Redundancy to Improve Computer Reliability”, IBM Journal of Research and Development, Vol. 6, No. 2, pp. 200-209, 1962.

  • W.W. Peterson, “On Checking an Adder”, IBM Journal of Research and Development, Vol. 2, No. 2, pp. 166-168, 1958.

  • E. Fujiwara and K. Haruta, “Fault-Tolerant Arithmetic Logic Unit using Parity-Based Codes”, IEICE Transactions, Vol. E64, No. 10, pp. 653-660, 1981.

  • F.W. Shih, “High Performance Self-Checking Adder Having Small Circuit Area”, U.S. Patent 5018093 A, May 21, 1991.

  • M. Nicolaidis, “Efficient Implementations of Self-Checking Adders and ALUs”, Proceedings of 23rd International Symposium on Fault-Tolerant Computing, pp. 586-595, 1993.

  • M. Nicolaidis, “On-Line Testing for VLSI: State of The Art and Trends”, Integration, the VLSI Journal, Vol. 26, No. 1-2, pp. 197-209, 1998.

  • B. Kiran Kumar and P.K. Lala, “On-Line Detection of Faults in Carry-Select Adders”, Proceedings of IEEE International Test Conference, pp. 912, 2003.

  • M.A. Akbar and J.-A. Lee, “Comments on “Self-Checking Carry-Select Adder Design Based on Two-Rail Encoding”, IEEE Transactions on Circuits and Systems-I: Regular Papers, Vol. 61, No. 7, pp. 2212-2214, 2014.

  • C. Pradeep, R. Radhakrishnan, R. Saranya and S. Philip, “Synthesis of Data Path Architecture with Online Fault Detection Mechanism for Reconfigurable Systems”, Australian Journal of Basic & Applied Sciences, Vol. 8, No. 10, pp. 239-245, 2014.

  • K. Yotmgjoon and L.-S. Kim, “A Low Power Carry Select Adder with Reduced Area”, Proceedings of IEEE International Symposium on Circuits and Systems, Vol. 4, pp. 218-221, 2001.

  • D.P. Vasudevan, P.K. Lala, Jia Di and J.P. Parkerson, “Reversible-logic design with online testability”, IEEE Transactions on Instrumentation and Measurement, Vol. 55, No. 2, pp. 406-414, 2006.


Abstract Views: 398

PDF Views: 0




  • High Speed Online Fault Detection of 64-Bit Ripple Carry Adder Using Modified Modular Redundancy

Abstract Views: 398  |  PDF Views: 0

Authors

Jisha M. Nair
Department of Electronics and Communication Engineering, Saintgits College of Engineering, India
C. Pradeep
Department of Electronics and Communication Engineering, Saintgits College of Engineering, India

Abstract


Developments in VLSI technology has increased density of chips so that, processing elements are capable of doing complex computations. The increase in complexity and density of the VLSI chip has made electronic systems more susceptible to defects. Therefore, testing and fault tolerance techniques are required to guarantee reliable operations of systems. Online fault detection techniques are active during normal operations. This paper proposes a novel online fault detection technique for 64-bit Ripple Carry Adder based on type of input data. A technique is developed to detect the single stuck-at faults that occur in the Ripple Carry Adder by using two rail checker. The design was modeled using Verilog HDL and simulated and synthesized in Xilinx ISE 14.5. A comparison is made by implementing the design in different FPGA devices. The results show that the proposed design has better device utilization and less delay in Virtex 5 FPGA. The proposed technique has only 16.2% delay overhead compared to simple Ripple Carry Adder without fault detection.

Keywords


Defect, Fault, FPGA, Online Fault Detection, Two Rail Checker.

References