ICTACT Journal on Microelectronics

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High Speed Online Fault Detection of 64-Bit Ripple Carry Adder Using Modified Modular Redundancy


Affiliations
1 Department of Electronics and Communication Engineering, Saintgits College of Engineering, India
     

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Developments in VLSI technology has increased density of chips so that, processing elements are capable of doing complex computations. The increase in complexity and density of the VLSI chip has made electronic systems more susceptible to defects. Therefore, testing and fault tolerance techniques are required to guarantee reliable operations of systems. Online fault detection techniques are active during normal operations. This paper proposes a novel online fault detection technique for 64-bit Ripple Carry Adder based on type of input data. A technique is developed to detect the single stuck-at faults that occur in the Ripple Carry Adder by using two rail checker. The design was modeled using Verilog HDL and simulated and synthesized in Xilinx ISE 14.5. A comparison is made by implementing the design in different FPGA devices. The results show that the proposed design has better device utilization and less delay in Virtex 5 FPGA. The proposed technique has only 16.2% delay overhead compared to simple Ripple Carry Adder without fault detection.

Keywords

Defect, Fault, FPGA, Online Fault Detection, Two Rail Checker.
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  • High Speed Online Fault Detection of 64-Bit Ripple Carry Adder Using Modified Modular Redundancy

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Authors

Jisha M. Nair
Department of Electronics and Communication Engineering, Saintgits College of Engineering, India
C. Pradeep
Department of Electronics and Communication Engineering, Saintgits College of Engineering, India

Abstract


Developments in VLSI technology has increased density of chips so that, processing elements are capable of doing complex computations. The increase in complexity and density of the VLSI chip has made electronic systems more susceptible to defects. Therefore, testing and fault tolerance techniques are required to guarantee reliable operations of systems. Online fault detection techniques are active during normal operations. This paper proposes a novel online fault detection technique for 64-bit Ripple Carry Adder based on type of input data. A technique is developed to detect the single stuck-at faults that occur in the Ripple Carry Adder by using two rail checker. The design was modeled using Verilog HDL and simulated and synthesized in Xilinx ISE 14.5. A comparison is made by implementing the design in different FPGA devices. The results show that the proposed design has better device utilization and less delay in Virtex 5 FPGA. The proposed technique has only 16.2% delay overhead compared to simple Ripple Carry Adder without fault detection.

Keywords


Defect, Fault, FPGA, Online Fault Detection, Two Rail Checker.

References