Open Access Open Access  Restricted Access Subscription Access
Open Access Open Access Open Access  Restricted Access Restricted Access Subscription Access

Area Optimized and Frequency Efficient 1024 Point Radix-2 FFT Processor on FPGA


Affiliations
1 ECED, Muffakham Jah College of Engineering and Technology, Hyderabad, Telangana, India
2 ECED, Bhoj Reddy Engineering College for Women, Hyderabad, Telangana, India
     

   Subscribe/Renew Journal


This paper presents optimized area and frequency efficient Fast Fourier Transform (FFT) processor using radix-2 Decimation in Time (DIT) algorithm. The proposed FFT processor is a complex FFT processor where a time-multiplexed approach to the butterfly of 1024 point, fixed, 32-bit, based on Field Programmable Gate Array (FPGA) is designed. The architecture is based on burst I/O and the pipelined-streaming I/O structure in the butterfly module and the ping-pong operation which is clocking at 480 MHz on Xilinx vertex 6 xc6vlx550t-2ff1759.

Keywords

Fast Fourier Transform, Field Programmable Gate Array, Ping-Pong Operation, Pipelined-Streaming I/O, Time-Multiplexed Butterfly.
User
Subscription Login to verify subscription
Notifications
Font Size

Abstract Views: 330

PDF Views: 4




  • Area Optimized and Frequency Efficient 1024 Point Radix-2 FFT Processor on FPGA

Abstract Views: 330  |  PDF Views: 4

Authors

Md. Ali Ghazi Islam
ECED, Muffakham Jah College of Engineering and Technology, Hyderabad, Telangana, India
Kazi Nikhat Parvin
ECED, Bhoj Reddy Engineering College for Women, Hyderabad, Telangana, India
Md. Zakir Hussain
ECED, Muffakham Jah College of Engineering and Technology, Hyderabad, Telangana, India

Abstract


This paper presents optimized area and frequency efficient Fast Fourier Transform (FFT) processor using radix-2 Decimation in Time (DIT) algorithm. The proposed FFT processor is a complex FFT processor where a time-multiplexed approach to the butterfly of 1024 point, fixed, 32-bit, based on Field Programmable Gate Array (FPGA) is designed. The architecture is based on burst I/O and the pipelined-streaming I/O structure in the butterfly module and the ping-pong operation which is clocking at 480 MHz on Xilinx vertex 6 xc6vlx550t-2ff1759.

Keywords


Fast Fourier Transform, Field Programmable Gate Array, Ping-Pong Operation, Pipelined-Streaming I/O, Time-Multiplexed Butterfly.