![Open Access](https://i-scholar.in/lib/pkp/templates/images/icons/fulltextgreen.png)
![Restricted Access](https://i-scholar.in/lib/pkp/templates/images/icons/fulltextred.png)
![Open Access](https://i-scholar.in/lib/pkp/templates/images/icons/fulltextgreen.png)
![Open Access](https://i-scholar.in/lib/pkp/templates/images/icons/fulltext_open_medium.gif)
![Restricted Access](https://i-scholar.in/lib/pkp/templates/images/icons/fulltextred.png)
![Restricted Access](https://i-scholar.in/lib/pkp/templates/images/icons/fulltext_restricted_medium.gif)
Area Optimized and Frequency Efficient 1024 Point Radix-2 FFT Processor on FPGA
Subscribe/Renew Journal
This paper presents optimized area and frequency efficient Fast Fourier Transform (FFT) processor using radix-2 Decimation in Time (DIT) algorithm. The proposed FFT processor is a complex FFT processor where a time-multiplexed approach to the butterfly of 1024 point, fixed, 32-bit, based on Field Programmable Gate Array (FPGA) is designed. The architecture is based on burst I/O and the pipelined-streaming I/O structure in the butterfly module and the ping-pong operation which is clocking at 480 MHz on Xilinx vertex 6 xc6vlx550t-2ff1759.
Keywords
Fast Fourier Transform, Field Programmable Gate Array, Ping-Pong Operation, Pipelined-Streaming I/O, Time-Multiplexed Butterfly.
User
Subscription
Login to verify subscription
Font Size
Information
![](https://i-scholar.in/public/site/images/abstractview.png)
Abstract Views: 292
![](https://i-scholar.in/public/site/images/pdfview.png)
PDF Views: 4