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Area Optimized and Frequency Efficient 1024 Point Radix-2 FFT Processor on FPGA
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This paper presents optimized area and frequency efficient Fast Fourier Transform (FFT) processor using radix-2 Decimation in Time (DIT) algorithm. The proposed FFT processor is a complex FFT processor where a time-multiplexed approach to the butterfly of 1024 point, fixed, 32-bit, based on Field Programmable Gate Array (FPGA) is designed. The architecture is based on burst I/O and the pipelined-streaming I/O structure in the butterfly module and the ping-pong operation which is clocking at 480 MHz on Xilinx vertex 6 xc6vlx550t-2ff1759.
Keywords
Fast Fourier Transform, Field Programmable Gate Array, Ping-Pong Operation, Pipelined-Streaming I/O, Time-Multiplexed Butterfly.
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