Open Access
Subscription Access
Open Access
Subscription Access
A Low Power DBI Based CRC Design Using GDI Technology
Subscribe/Renew Journal
In this paper, we implemented the data bus inversion cyclic redundancy check using Gate Diffusion input technique. Initially to reduce signaling power in the single-ended interface Data Bus Inversion (DBI) is required, in which the state of the data to be transmitted may or may not be inverted prior to transmission. a new CRC methodology which is based on the DBI is to reduce the CRC calculation delay time and area overhead for high-speed memory devices. GDI logic is introduced as an alternative to CMOS logic. It is a low power design technique which offers the implementation of the logic function with fewer numbers of transistors. GDI gates provide reduced voltage swing at their outputs. In GDI based CRC no of transistors are reduced and power consumption and area is decreased.
Keywords
Cyclick Redundency Check, Data Bus Inversion, Gate Diffusion Input.
User
Subscription
Login to verify subscription
Font Size
Information
- J.-H. Lee, “Implementation in high-speed semiconductor memory,” 8th International Conference on Control and Automation, IEEE, DOI 10.1109/CA.2015.13, 2015.
- K. Koo, S. Ok, Y. Kang, S. Kim, C. Song, H. Lee, H. Kim, Y. Kim, J. Lee, S. Oak, Y. J. M. Lee, J. Jang, J. C. Jung, B. Choi, Y. Hur, and B. T. Chung, “A 1.2V 38nm 2.4Gb/s/pin 2Gb DDR4 SDRAM with bank group and x4 half-page architecture,” IEEE International Solid State Circuits Conference, San Francisco, California, USA, pp. 40-41, 19-23 Feb. 2012.
- S. Yoon, B. Kim, Y. Kim, and B. Chung, “A fast GDDR5 read CRC calculation circuit with read DBI operation,” IEEE Asian Solid-State Circuits Conference, Fukuoka, pp. 249-252, 2-5 Nov. 2008.
- S. J. Bae, and K.-I. Park, “An 80 nm 4 Gb/s/pin 32 bit 512 Mb GDDR4 graphics DRAM with low power and low noise data bus inversion,” IEEE Journal of Solid-State Circuits, vol. 43, no.1, pp. 121-131, 2008.
- J. Moon, “Fast parallel CRC & DBI calculation for high-speed memories: GDDR5 and DDR4,” IEEE International Symposium, Circuits and Systems (ISCAS), Rio de Janeiro, Brazil, pp. 317-320, 15-19 May, 2011.
- V. G. Oklobdzija, and D. Villeger, “Improving multiplier design using improved column compression tree and optimized final adder in CMOS technology,” IEEE Trans. VLSI Syst., vol. 3, no. 2, pp. 292-301, 1995.
- A. M. Shams, D. K. Darwish, and M. A. Bayoumi, “Performance analysis of low power 1-bit CMOS full adder cells,” IEEE Trans. VLSI Syst., vol. 10, no. 1, pp. 20-29, 2002.
- M. Maeen, V. Foroutan, and K. Navi, “On the design of low power 1-bit full adder cell,” IEICE Electron. Expr., vol. 6, no. 16, pp. 1148-1154, 2009.
- R. Patel, H. Parasar, and M. Wajid, “Faster arithmetic and logical unit CMOS design with reduced number of transistors,” Proc. of Intl. Conf. on Advances in Communication, Network and Computing, vol. 142, pp. 519-522, 2011.
- P. M. Lee, C. H. Hsu, and Y. H. Hung, “Novel 10-T full adders realized by GDI structure,” Proc. IEEE International Symposium on Integrated Circuits (ISIC), pp. 115-118, 2007.
- K. K. Chaddha, and R. Chandel, “Design and analysis of a modified low power CMOS full adder using gate-diffusion input technique,” Journal of Low Power Electronics, vol. 6, no. 4, pp. 482-490, 2010.
- A. Morgenshtein, A. Fish, and I. A. Wagner, “Gate Diffusion Input (GDI): A power efficient method for digital combinatorial circuits,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 10, no. 5, pp. 566-581, 2002.
Abstract Views: 375
PDF Views: 7