Design and Implementation of Booth Multiplier and Its Application Using VHDL

Low power consumption and small area are some of the most important criteria for design of any high performance systems. So in this paper the best solution to the problem is determined by designing a high speed multiplier chiefly booth multiplier which reduces the number of flip flops and memory size in the design circuitry as compared to conventional serial multiplier. Then implementation of a calculator using booth multiplier and several other operational modules is done using codes written in VHDL language using ISE XILINX 6.1 and simulated in MODEL SIM 5.4a.