International Journal of Scientific Engineering and Technology

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Employing Functional Analysis to Study Fault Models in VHDL


Affiliations
1 SET, Jain University, Bangalore, India
2 7 Star Technologies, Bangalore, India
3 Allied Tools and Electronics, Bangalore, India
4 Signal Processing and VLSI, SET, Jain University, Bangalore, India
 

In this paper, VHDL & functional analysis is used to model and to study the effect of faults on gate level circuits respectively. The model is developed via abstraction of industry standard single stuck line (SSL) faults into the behavioral domain and the effects of these faults on gate level circuits are discussed.

Keywords

Fault Models, Behavioral Modeling, VHDL, Functional Analysis, RTL Synthesis, Stuck Faults.
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  • Employing Functional Analysis to Study Fault Models in VHDL

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Authors

N. Venkatesh Kumar
SET, Jain University, Bangalore, India
Mujeeb Ulla Jeelani
7 Star Technologies, Bangalore, India
V. Amritha Mulay
Allied Tools and Electronics, Bangalore, India
Anoop S. Shandilya
Signal Processing and VLSI, SET, Jain University, Bangalore, India

Abstract


In this paper, VHDL & functional analysis is used to model and to study the effect of faults on gate level circuits respectively. The model is developed via abstraction of industry standard single stuck line (SSL) faults into the behavioral domain and the effects of these faults on gate level circuits are discussed.

Keywords


Fault Models, Behavioral Modeling, VHDL, Functional Analysis, RTL Synthesis, Stuck Faults.