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An Efficient Design of Sequential Digital Circuits to Reduce Soft Errors in Nanoscale CMOS Technology


Affiliations
1 M.Tech. Student, Department of E.C.E., K.L. University, Guntur Dt., A.P.,, India
2 Dept. of ECE, K.L. University, Vijayawada, India
     

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We initiate some soft-error-tolerant Sequential elements which evaluate the benefits and drawbacks of several state-of-the-art designs, and determines optimal designs for advanced technology. The designs induce non-trivial area, power overhead. In modern technologies, logic elements are becoming increasingly vulnerable to soft errors. Several designs today implement extensive error detection and correction. In this design we use smaller and faster transistors. In this work, we will analyze the impact of soft errors on latches and flip-flops in nanoscale CMOS technology. Here each design is compared with a standard, non-SER tolerant latch or flip-flop, and then assess each design based on SER protection, area, and power overhead.

Keywords

Reliability, Soft Error, SER, Nanoscale Cmos
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  • An Efficient Design of Sequential Digital Circuits to Reduce Soft Errors in Nanoscale CMOS Technology

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Authors

K. Aditya
M.Tech. Student, Department of E.C.E., K.L. University, Guntur Dt., A.P.,, India
M. Sivakumar
Dept. of ECE, K.L. University, Vijayawada, India
B.K.V. Prasad
Dept. of ECE, K.L. University, Vijayawada, India
Syed Inthiyaz
Dept. of ECE, K.L. University, Vijayawada, India

Abstract


We initiate some soft-error-tolerant Sequential elements which evaluate the benefits and drawbacks of several state-of-the-art designs, and determines optimal designs for advanced technology. The designs induce non-trivial area, power overhead. In modern technologies, logic elements are becoming increasingly vulnerable to soft errors. Several designs today implement extensive error detection and correction. In this design we use smaller and faster transistors. In this work, we will analyze the impact of soft errors on latches and flip-flops in nanoscale CMOS technology. Here each design is compared with a standard, non-SER tolerant latch or flip-flop, and then assess each design based on SER protection, area, and power overhead.

Keywords


Reliability, Soft Error, SER, Nanoscale Cmos

References