Development of High Density through the Wafer Vias Using Drie Based Micromachining

Fabrication of deep silicon vias in silicon for the feasibility of three dimensional (3-D) MEMS structures faces multiple technological process challenges before it can become a commercially viable technology. One of the key fabrication step required is the deep silicon etching for forming high aspect ratio structures. This technology can be easily integrate in the conventional process flow during siliconization of the device. There is an increasing interest among the researchers in the use of dry plasma etching for this application because of its anisotropic etching behavior, high etch speed, good uniformity, profile control and high aspect ratio capabilities without causing any undesired secondary effects. In-house high-density through-wafer vias process is being developed at Semi-Conductor Laboratory. The aim is to achieve cost-effective vertical interconnects CMOS compatible that are easily integrated into a device process flow. Deep reactive ions etch (DRIE) process was developed to etch 50 μm dia via holes through 675 μm thick silicon wafers. The DRIE BOSCH process was optimized to carry out through and through via holes in silicon. Further, a thin gold (Au/Ti) metal layer was deposited as a seed layer in the vias and afterwards these vias Au layer filling is carried out using the electroplating technology to be used as conductive material. A novel in house process was developed using DRIE for achieving the desired aspect ratio of 14:1 required for realization of high density via holes. Detailed process steps are discussed in this article which can be utilized for various via dimensions as per the application requirements. Also role of various parameters and its effects are given in this article.