Synthesis and Analysis of 32-Bit RSA Algorithm Using VHDL

This paper presents the implementation of RSA algorithm design using VHDL. The Xilinx ISE 14.1 is used with device Spartan-3. In [1], the RSA encryption technique is implemented by using right to left binary radix-2 montmgomery multiplier. This paper presents the implementation of encryption technique by using left to right radix-2 montmgomery multiplier. The modular exponentiation is used for encryption and decryption of RSA algorithm. The device utilization is improved by 14%. The delay is improved by 2%. The frequency of the implementation is 79.546 MHz and is increased by 4.5%. Hence, the presented work is area and delay efficient than previous work.