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Survey on Power Minimization Techniques in Digital Systems


Affiliations
1 Department of Electronics and Communication Engineering, Punjabi University, Patiala, India
 

Power has become one of the circuit implementation bottleneck for modern integrated design. As technology advances, system on chip can have more and more components that lead to higher power density. This paper includes the survey onvarious techniques used for implementation of low power systems.

Keywords

Integrated Design, System on Chip, Power Density, Low Power Systems.
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  • Survey on Power Minimization Techniques in Digital Systems

Abstract Views: 174  |  PDF Views: 1

Authors

Ramanpreet Kaur
Department of Electronics and Communication Engineering, Punjabi University, Patiala, India
Gurmeet Kaur
Department of Electronics and Communication Engineering, Punjabi University, Patiala, India

Abstract


Power has become one of the circuit implementation bottleneck for modern integrated design. As technology advances, system on chip can have more and more components that lead to higher power density. This paper includes the survey onvarious techniques used for implementation of low power systems.

Keywords


Integrated Design, System on Chip, Power Density, Low Power Systems.