Design and Analysis of 32 Bit Regular and Improved Square Root Carry Select Adder

In modern VLSI technology transistors size is shrinking day by day for increasing speed and to reduce chip size, performance degradation is one of the major issues. As the technology scale down leakage power dissipation increases exponentially. In this paper a comparison among different parameters of square ischolar_main carry select adders has been presented. These two 32 bit square ischolar_main carry select adders are designed at 32nm technology. Performance of these sqrt carry select adders are evaluated and analysed in terms of delay, average power dissipation, power delay product and transistor count. Simulations are performed at 1.1v, with transistor length at 32nm. Their analysis reveals that improved 32 bit sqrt carry select adder has lesser delay, PDP as well as transistor count as compared to regular 32 bit sqrt carry select adder.