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Design of High Performance Digital Fir Filter Using Distributed Arithmetic Algorithm with Residue Number System


Affiliations
1 Gurukul Institute of Engineering and Technology, Kota, India
2 Department of Electronics and Communication Engineering, S.R.M. University Kattankuluthar, India
3 Maharishi Arvind International Institute of Technology, Kota
4 St. Margaret Engineering College, Neemrana, India
5 Rajasthan Technical University, Kota, India
     

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The use of the proposed method in residue to binary conversion in Residue Number System (RNS) and Distributed Arithmetic Algorithm (DAA) in modern telecommunication and multimedia applications is becoming more and more important because it allows interesting advantages in terms of area, power consumption and speed.. This paper presents new method for conversion procedure (residue to binary) based on a {2n -1,2n , 2n+1, 2n + 1+1, 2n - 1 -1} moduli set. Based on the proposed method for conversion in RNS and DAA algorithm, an architecture which efficiently implements the digital fir filter is synthesized using Xilinx Virtex2. Proposed method simplify the computing procedure by maximizing the utilization of the modulo-mi adders and multipliers present in the RNS functional units. For an n-digit RNS number X = (x1, x2, x3, …., xn) the proposed method takes at most n iterations. Each iteration requires one parallel subtractions and 2 multiplications except the first one.

Keywords

Residue Arithmetic, Distributed Arithmetic, Fir Filters, High Speed, VLSI.
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  • Design of High Performance Digital Fir Filter Using Distributed Arithmetic Algorithm with Residue Number System

Abstract Views: 252  |  PDF Views: 1

Authors

Antim Bala Sharma
Gurukul Institute of Engineering and Technology, Kota, India
T. Vigneswaran
Department of Electronics and Communication Engineering, S.R.M. University Kattankuluthar, India
Ajay Sharma
Maharishi Arvind International Institute of Technology, Kota
Fanibhushan Sharma
St. Margaret Engineering College, Neemrana, India
Nirmala Sharma
Rajasthan Technical University, Kota, India

Abstract


The use of the proposed method in residue to binary conversion in Residue Number System (RNS) and Distributed Arithmetic Algorithm (DAA) in modern telecommunication and multimedia applications is becoming more and more important because it allows interesting advantages in terms of area, power consumption and speed.. This paper presents new method for conversion procedure (residue to binary) based on a {2n -1,2n , 2n+1, 2n + 1+1, 2n - 1 -1} moduli set. Based on the proposed method for conversion in RNS and DAA algorithm, an architecture which efficiently implements the digital fir filter is synthesized using Xilinx Virtex2. Proposed method simplify the computing procedure by maximizing the utilization of the modulo-mi adders and multipliers present in the RNS functional units. For an n-digit RNS number X = (x1, x2, x3, …., xn) the proposed method takes at most n iterations. Each iteration requires one parallel subtractions and 2 multiplications except the first one.

Keywords


Residue Arithmetic, Distributed Arithmetic, Fir Filters, High Speed, VLSI.