Design and Analysis of CMOS J-K Flip-Flop and Basic Adiabatic Circuits

This paper, presents the design of CMOS based J-K flip-flop and ECRL (Efficient Charge Recovery Logic) based inverter and basic AND logic gate using adiabatic technique. The ECRL is more suitable for the design of flip-flops and sequential circuits, as it uses fewer transistors than the conventional CMOS implementation and other adiabatic techniques. Design of ECRL based adiabatic J-K flip-flop using MICROWIND 3.5 tool with 25 nm technology is also proposed. VERILOG simulations show that the energy loss of the adiabatic circuits is greatly reduced as compared to the conventional CMOS implementation.