International Journal of Science, Engineering and Computer Technology

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Design Technique Of Low Voltage CMOS OP-AMP


Affiliations
1 Research Scholar, School of Electronics & Electrical Engineering, Singhania University, Rajasthan
     

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In this paper low power CMOS Op-Amp operating with low supply voltage is described. It will begin by presenting one of the traditional low voltage CMOS Op-Amp design techniques such as folded cascode structure and then describe some more recent developments in Op-Amp design such as floating gate and bulk driven CMOS Op-Amps.

Keywords

Design Technique,low Voltage
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  • Design Technique Of Low Voltage CMOS OP-AMP

Abstract Views: 317  |  PDF Views: 0

Authors

Vinod Kumar
Research Scholar, School of Electronics & Electrical Engineering, Singhania University, Rajasthan

Abstract


In this paper low power CMOS Op-Amp operating with low supply voltage is described. It will begin by presenting one of the traditional low voltage CMOS Op-Amp design techniques such as folded cascode structure and then describe some more recent developments in Op-Amp design such as floating gate and bulk driven CMOS Op-Amps.

Keywords


Design Technique,low Voltage