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Parallel Hardware Implementation of Walsh Hadamard Transform


Affiliations
1 Department of ECE, Regent Education and Research Foundation, Kolkata 700 121, West Bengal, India
2 Department of ETCE, Jadavpur University, Kolkata 700 032, West Bengal, India
3 Department of Electronics and Communication Engineering, MCKV Institute of Engineering, Howrah 711 104, India
4 Department of ECE, Birla Institute of Technology, Mesra, Ranchi 835 215, Jharkhand, India

The Walsh Hadamard Transform is a powerful notion in digital signal processing. This paper explains the construction of parallel hardware architecture using the mathematical concept of Kronecker product based approach to Walsh Hadamard Transform and its simulation using Verilog. This architecture is simulated here using Field Programmable Gate Array (FPGA) technology in Verilog Spartan 3e platform. Furthermore, this paper illustrates the fast algorithm and parallel computational result of both one-dimensional and two-dimensional transforms using the Kronecker product.This algorithm can be used to implement a systolic array based dedicated hardware for computation of the transform. Our proposed hardware design for the Walsh Hadamard Transform will be used in various digital signal processing applications. The systematic derivation of parallel architecture design using the concept of Kronecker product and stride permutation would depict the real time processing rather than conventional way and reducing time complexity using minimal resources is a challenging task.
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  • Parallel Hardware Implementation of Walsh Hadamard Transform

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Authors

Pulak Mazumder
Department of ECE, Regent Education and Research Foundation, Kolkata 700 121, West Bengal, India
Soumyadeep Chandra
Department of ETCE, Jadavpur University, Kolkata 700 032, West Bengal, India
Sekhar Rana
Department of Electronics and Communication Engineering, MCKV Institute of Engineering, Howrah 711 104, India
Mainak Mukhopadhyay
Department of ECE, Birla Institute of Technology, Mesra, Ranchi 835 215, Jharkhand, India
Mrinal Kanti Naskar
Department of ETCE, Jadavpur University, Kolkata 700 032, West Bengal, India

Abstract


The Walsh Hadamard Transform is a powerful notion in digital signal processing. This paper explains the construction of parallel hardware architecture using the mathematical concept of Kronecker product based approach to Walsh Hadamard Transform and its simulation using Verilog. This architecture is simulated here using Field Programmable Gate Array (FPGA) technology in Verilog Spartan 3e platform. Furthermore, this paper illustrates the fast algorithm and parallel computational result of both one-dimensional and two-dimensional transforms using the Kronecker product.This algorithm can be used to implement a systolic array based dedicated hardware for computation of the transform. Our proposed hardware design for the Walsh Hadamard Transform will be used in various digital signal processing applications. The systematic derivation of parallel architecture design using the concept of Kronecker product and stride permutation would depict the real time processing rather than conventional way and reducing time complexity using minimal resources is a challenging task.