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VLSI Implementation of Area-Efficient and Low Power OFDM Transmitter and Receiver


Affiliations
1 VLSI Design, Sathyabama University, Chennai - 600119, Tamil Nadu, India
 

Background: This paper consists of an analysis of Fast Fourier Transform (FFT) architectures which are the backbone of any OFDM based wireless networks. Methods: By using the FFT concepts we are indeed in developing an efficient architectures for wireless networks which are common in everywhere now-a-days, Our concepts are purely based upon in development we have to test it by using Field Programmable Gate Array (FPGA),we are using Xilinx based Spartan-3e FPGA. Results: The concepts are simulated by using Modelsim6.3c and to synthesize by using Xilinx ISE 10.1.

Keywords

FFT, FPGA, OFDM, SDF-SDC
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  • VLSI Implementation of Area-Efficient and Low Power OFDM Transmitter and Receiver

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Authors

D. Kalaivani
VLSI Design, Sathyabama University, Chennai - 600119, Tamil Nadu, India
S. Karthikeyen
VLSI Design, Sathyabama University, Chennai - 600119, Tamil Nadu, India

Abstract


Background: This paper consists of an analysis of Fast Fourier Transform (FFT) architectures which are the backbone of any OFDM based wireless networks. Methods: By using the FFT concepts we are indeed in developing an efficient architectures for wireless networks which are common in everywhere now-a-days, Our concepts are purely based upon in development we have to test it by using Field Programmable Gate Array (FPGA),we are using Xilinx based Spartan-3e FPGA. Results: The concepts are simulated by using Modelsim6.3c and to synthesize by using Xilinx ISE 10.1.

Keywords


FFT, FPGA, OFDM, SDF-SDC



DOI: https://doi.org/10.17485/ijst%2F2015%2Fv8i18%2F113442