Design of Enhanced Half Ripple Carry Adder for VLSI Implementation of Two-Dimensional Discrete Wavelet Transform

The aim of the current research work is to design an efficient two-dimensional Discrete Wavelet Transformation (DWT) based image compression technique. In order to achieve best performance, Enhanced Half-Ripple Carry Adder (EHRCA) has been designed. Verilog Hardware Description Language (Verilog HDL) is used to model the EHRCA and DWT technique. DWT technique has been designed with the help of two types of filtering technique known as Low Pass Filter (LPF) and High Pass Filter (HPF). Three levels of decomposition is made by DWT process and each process have two levels compressions called “Row Wise Compression” and “Column Wise Compression”. In proposed DWT models, adders are recognized as high potential than other components. In order to improve the efficiency of DWT process, an efficient adder called “Enhanced Half-Ripple Carry Adder (EHRCA)” has been designed in this research work. Proposed EHRCA circuit offers 10.71% improvements in hardware slice utilization, 11.78% improvements in total power consumption than traditional Binary to Excess 1 Conversion (BEC) based Square Root Carry Select Adder (SQRT CSLA). Further proposed adder has been incorporated into Row Wise Compression and Column Wise Compression for improving the architectural performances of DWT. In future, proposed EHRCA based DWT will be useful in Discrete Cosine Transformation (DCT) and hybrid type and lifting based DWT techniques.