Enhanced MixColumn Design for AES Encryption

The main aim of the current research work is to reduce the complexity path of AES (Advanced Encryption Standard) Encryption. Architecture of MixColumn transformation has been optimized in this research work. Traditional methods of MixColumn transformation methods has been realized and re-designed by reducing the redundant logical functions. Verilog Hardware Description Language (Verilog HDL) has been used to design the optimized MixColumn transformation of AES Encryption. Further optimized MixColumn design has been incorporated into AES Encryption with appropriate input points. Common Sub-expression Elimination (CSE) algorithm is used in developed AES Encryption algorithm. Proposed optimized MixColumn design offers 10.93% improvements in hardware slices, 13.6% improvements in LUTs and 1.19% improvements in delay consumption than traditional MixColumn design. Further proposed optimized MixColumn design has been incorporated into AES Encryption design. Further, proposed optimized MixColumn based AES Encryption design offers 4.75% improvements in silicon area, 4.56% reduction in power consumption than traditional MixColumn based AES Encryption. In future, proposed optimized MixColumn design will be useful in space and terrestrial applications for exhibiting secure transmissions.