Design of Reversible Number Generator using Finite State Automation Realization

Objective: The objective of this paper is to realize an n-bit reversible number generator. Several designs of number generator and their corresponding constraints with feedback controller and initial state have also been discussed. Method/Analysis: The proposed design is validated by simulating the results in Verilog HDL. Findings: In this paper a design is presented to implement an n bit number generator as a finite state automation, using reversible logic for the implementation of the transition network. A realizable circuit is designed to implement the n-bit number generator using feedback controllers. Novelty/Improvement: With the use of reversible logic, the designed circuit reaches all the possible states and consumes no power.