Implementation of High Throughput Extended Tiny Encryption Algorithm Block Cipher in Field Programmable Gate Array

The main objective of the paper is to improve the throughput and increase the speed of the XTEA (Extended Tiny Encryption Algorithm) which is one of the cryptographic algorithms. The technique used to improve the throughput is parallel processing. In previous, they have used pipelining which increases the overhead that is not desirable. The error detection scheme employed in this paper is RERO (Recomputing with Rotated Operand). The previous error detection REPO (Recomputing with Permuted Operands) occupies more memory than RERO. The embedded systems have been developing with many sensitive nodes like Nano-sensors, Radio Frequency Identification tags, etc. As these systems have many constraints, the required security is given by the light weight block ciphers like PRESENT, XTEA and SIMON. These block ciphers are more suitable for these embedded systems when compared to Advanced Encryption Standard (AES). Providing security alone does not give assurance for their reliability while these architectures are liable to malicious and natural faults. Due to hardware failures, various types of faults occur while implementing in hardware. To overcome this, there are many schemes for error detection that can be applied to these ciphers. One of the error detection schemes is RERO (Recomputing with Rotated Operands). Through RERO, error coverage is achieved high. Parallel processing is applied to the XTEA algorithm to increase the throughput. The two halves that are used in the XTEA algorithm are executed at the same time through the parallel processing. Finally, this algorithm is implemented in the Altera FPGA (Field Programmable Gate Array). The throughput is increased by 60% when compared to previous systems that use sub pipelining. This type of structure finds its application in low resource embedded systems having sensitive nodes like RFID tags and Nano sensors