Study and Analysis of CMOS Carry Look Ahead Adder with Leakage Power Reduction Approaches

Background/Objectives: This paper represents the implementation of carry look ahead adder using different leakage power reduction techniques like sleepy approach, stack approach, sleepy stack approach and sleepy keeper approach. Effecting the static power dissipation high, the threshold voltage (Vth) is reduced that has granted tremendously towards the growth in the sub threshold leakage power. Here conventional 4-bit carry look ahead adder is designed by adopting 1-bit full adders and carry look ahead blocks. Methods/Statistical Analysis: In this paper, an extensive study and analysis of different leakage power minimization approaches have been implemented. In the comparative analysis carry look ahead adder is designed using different leakage power reduction approaches like sleepy, stack, sleepy stack and sleepy keeper. The circuits are implemented on Tanner EDA tool at 250 nm Technology and considered PMOS, NMOS as typical models. From this paper work that only an applicable selection of leakage power reduction approach for a particular function will be well borne by a Very Large Scale Integrated (VLSI) circuit design depend on progressive analytical method. Findings: The average power, delay and number of transistors are calculated in the tanner tool for carry look ahead adder using all the four approaches. Applications/Improvements: The analytical study is implemented in the real time applications while constructing adders.