An Efficient Design of Sub-threshold Logic Circuits for Ultra Low Power VLSI Applications

In this paper, we have provided one of the solutions for achieving ultra-low power goals. The technique used is Subthreshold region operation. This technique is useful in the applications where speed is of the secondary importance, and the low power requirement is of the prime concern. We have designed an ultra-low power sub-threshold circuits in which the voltage scaling is done below the threshold voltages. The reduction in energy consumption comes at the cost of the circuit performance. We analyzed the CMOS circuits in normal as well as sub-threshold regions and the results prove that there are orders of magnitude reduction in the power consumption.