Variable Latency Approach in VLSI Adder Implemented to Reduce Area and Power

Objective: The Ultimate aim of the VLSI Design is to improve the efficiency, Reduction of Delay and Power Consumption and to minimize the area. In our proposed approach we had implemented the analysis had been done on the field of Speed, Power consumption, Area and Power delay product (PDP) for a carry skip adder with other adders listed as the parallel prefix adders and others. Methods/Statistical Analysis: The Carry-Skip Adder planned here reduces the time required to propagate the carry by skipping over teams of consecutive adder stages, is understood to be comparable in speed to the carry look-ahead technique whereas it uses less logic space and fewer power. Findings: The adders are basic building blocks of the digital circuits for the Signal processing, Integrating and other process of operation. There are various types of adders are proposed in Literature which are commonly used in VLSI Design. The Simulation results also shows that the proposed adder Architecture is Faster and Area efficient compared to other existing adder architecture. Application/ Improvements: They estimate the performance of proposed design will be better in terms of Logic and route delay by experimental results.