Optimization of Power and Area in Multipliers for Image Processing Applications

Objectives: This paper is aimed to find a multiplier to provide a physically compact high speed and low power consumption unit. Being a core part of arithmetic processing unit multipliers are in extremely high demand on its speed and low power consumption. Multiplier plays an important role in today’s digital image processing and various other applications. Methods/Statistical Analysis: In modern embedded electronics devices, power consumption is a first-class design concern. Hardware-level approximation mainly targets arithmetic units, such as adders and multipliers, widely used in portable devices to implement multimedia algorithms, e.g., image and video processing. Findings: Compressor has 5 inputs A, B, C, D and C_in to create 3 outputs Sum, Carry and C_out. The 4 inputs A, B, C and D and the output Sum has identical weight. The input C_in is output from a preceding lower widespread compressor and the C_out output is for the compressor inside the next significant level. Application/Improvements: The approximation multiplier is used to improve the speed and efficiency. It is used to reduce the area and time consumption. It is widely used in the digital image processing, FIR filters, reduce the multiplication procedure.